# Physical layer The mechanism to transmit information over a physical medium like a copper wire can be analyzed using two different worldviews: voltages and currents or electromagnetic waves. A digital system designer benefits from deeply knowing both and from choosing to apply one or another depending on the situation and the analysis being performed. At low frequencies, such as those typically found in power distribution (50 Hz or 60 Hz) or a few kilohertz, the wavelength of the electromagnetic wave is very long compared to the length of the interconnect (the electromagnetic wavelength is the distance between consecutive peaks or troughs of an electromagnetic wave). In these cases, the voltage and current are practically uniform along the length of the line at any instant, and the concept of a wave propagating down the line is not particularly useful. The interconnect can be modeled using circuit theory with lumped elements (resistors, capacitors, and inductors) which assume a uniform distribution of voltage and current along their length. However, as the frequency increases, the wavelength of the electromagnetic waves becomes shorter[^12] and can be comparable to or even shorter than the physical length of the interconnect that links transmitter and receiver. Under these conditions, the voltage and current at any point along the line can vary significantly from those at other points. This is particularly true for high-frequency signals. In these high-frequency scenarios, the interconnect must be strictly analyzed as a distributed system of sorts where the concepts of inductance, capacitance, resistance, and conductance are no longer valid (at least they cannot be considered lumped anymore), but they must be considered distributed along the line's length. The specific frequency at which this becomes important varies based on the physical dimensions of the interconnect and the properties of the surrounding materials. > [!rule of thumb] > If the propagation delay of the cable is greater than 1/8 the transition (rise or fall times of the signal, see figure below) the interconnect cannot be considered lumped anymore, and some other methods must be used to analyze it.  > [!Figure] > _A digital signal rise and fall times, and bit duration (or width)_ How do we calculate the propagation delay for a signal? It greatly depends on the medium the material propagates through. Let's use a typical interconnect used in digital systems: a [[Printed Circuit Boards|PCB]] microstrip in FR4 material. The propagation speed of a signal in an FR4 microstrip depends on the dielectric constant of the FR4 material. FR4 is a common substrate material used in printed circuit boards and typically has a dielectric constant from around 3.8 to 4.8, depending on the glass weave style, thickness, resin content, and copper foil roughness. The speed at which a signal propagates along a transmission line depends on the material's relative permittivity, also known as dielectric constant (Dk). The higher the Dk, the slower the signal propagation. The speed of a signal in a microstrip interconnect is slower than the speed of light in a vacuum due to the dielectric material's influence. The speed of the signal $\text{v\ }$in a microstrip can be calculated using the formula: $v = \LARGE\frac{c}{\sqrt{\varepsilon_{\text{eff}}}}$ Where: $\large\text{c\ }$ is the speed of light in vacuum which is approximately $3 \times 10^{8}$ meters per second. $\large\varepsilon_{\text{eff}}$ is the effective dielectric constant, which is a value between 1 and the dielectric constant of the FR4 material. The effective dielectric constant $\large\varepsilon_{\text{eff}}$ takes into account geometric aspects of interconnect and the dielectric constant of the substrate. > [!info] The approximate propagation speed of a signal in an FR4 microstrip is approximately 15 centimeters (6 inches) per nanosecond. This value is a simplified estimate and can vary based on the specific characteristics of the FR4 material and the design. We will come back to this number a few times during our analysis of interconnects and signals.  > [!Figure] > _Transmission Line equivalent circuit with lumped elements_ ## Interconnects When lumped elements are not useful anymore, the physical channel connecting a transmitter and a receiver is more accurately called a transmission line and, in reality, it acts as a guide for electromagnetic waves whose behavior is described by Maxwell's equations. Being uncomfortable about the notion of forces somehow acting on things situated at a distance, with nothing in between to communicate it, Maxwell chose to look at electromagnetic phenomena as manifestations of stresses and strains in a continuous elastic medium (later called the electromagnetic ether) that we are quite unaware of, yet which fills all the space in the universe (this is just a conceptual construction which would be later debunked by the [Michelson-Morley experiment](https://en.wikipedia.org/wiki/Michelson%E2%80%93Morley_experiment)). Using this idea, Maxwell was able to develop an essentially mechanical model of all the effects Faraday had observed so carefully. His picture had the disadvantage that along with physically real things like $\mathbf{E}$ (electric field in volts/meter) and $\mathbf{H}$ (magnetomotive force in amp turns/meter) it also uses concepts like $\mathbf{B}$ (flux) and $\mathbf{D}$ (displacement) which have no real physical existence (we will discuss these soon). Nevertheless, it worked, predicting accurately all the electromagnetic effects that could be observed in his time, and it still works in the majority of situations, of course, although as we now know it will fail where quantum effects become significant. But what are electromagnetic waves from Maxwell's point of view? Electromagnetic waves arise whenever charges accelerate, such as in an oscillating current. This motion generates a time-varying electric field, which in turn induces a magnetic field. The magnetic field, as it changes, regenerates the electric field. This continuous interplay allows the wave to propagate through space, even in the absence of a medium. The equations in the next section will explain this interplay. The electric field component of the wave is a vector quantity that oscillates in one plane, while the magnetic field oscillates in a plane perpendicular to it. Both fields are in phase, meaning their maxima and minima occur at the same points in time and space. The direction in which the wave travels is perpendicular to both the electric and magnetic fields, forming a three-dimensional relationship. Electromagnetic waves do not require a medium to travel, so they can propagate through a vacuum at the speed of light ($\approx 3 \times 10^8$ meters per second). Their wavelength and frequency determine their characteristics, such as whether they are visible light, radio waves, X-rays, or another form of electromagnetic radiation. ### Maxwell's Equations Maxwell's equations are a set of four fundamental laws that describe the behavior of electric and magnetic fields and their interactions with matter. They can be expressed in both integral and differential forms. Here's a brief overview of each in their time-varying differential form, which is most commonly used in physics and engineering: Gauss's Law for Electricity: $\large\nabla \cdot \mathbf{E} = \frac{\rho}{\varepsilon_{0}}$ This equation states that the divergence[^13][^14] of the electric field $\text{(}\mathbf{E}\text{)}$ is proportional to the electric charge density $\rho$ at that point, whereas $\varepsilon_{0}$ is the permittivity of free space. It essentially tells us that electric charges are sources of an electric field. Gauss's Law for Magnetism: $\large\nabla \cdot \mathbf{B} = 0$ This states that the divergence of the magnetic field $\text{(}\mathbf{B}\text{)}$ is zero, implying there are no "magnetic charges" analogous to electric charges, and magnetic field lines are closed loops. In other words, there are no magnetic monopoles. Faraday's Law of Induction: $\large\nabla \times \mathbf{E} = - \frac{\partial\mathbf{B}}{\partial t}$ Faraday's law indicates that a time-varying magnetic field creates (induces) a circulating electric field. Ampère's Law with Maxwell's addition: $\large \nabla \times \mathbf{B} = \mu_{0}\mathbf{J} + \mu_{0}\varepsilon_{0}\frac{\partial\mathbf{E}}{\partial t}$ This enhanced version of Ampères Law by Maxwell states that a current creates circulating magnetic field lines, and it includes an additional contributor to the magnetic field lines created: the displacement current, $\large \mu_{0}\varepsilon_{0}\partial E\text{/}\partial t$. What is this displacement current? This is quite important for the discussion about interconnects between transmitters and receivers that will keep us busy for a while so let's discuss displacement current a bit further. James Maxwell introduced the concept of displacement current to Ampères Law for it to account for changing electric fields in cases where there is no actual movement of charge, such as in a capacitor. In a capacitor, an electric field exists between two plates separated by a dielectric (an insulating material). When the electric field in the capacitor changes (for instance, when the capacitor is charging or discharging), there is a change in the electric displacement field $D$. The displacement field is related to the electric field $E$ and is given by $D = \epsilon E$, where $\epsilon$ is the permittivity of the material between the plates. Maxwell observed that even though there is no actual current flowing through the dielectric (since it's an insulator and does not allow charge to flow), the changing electric field can still influence magnetic fields, just like a real current would. To account for this phenomenon, he proposed the concept of a "displacement current", which is not a current of real charges, but a term added to represent the rate of change of the electric field. In the case of a capacitor, as it charges or discharges, the displacement current is what "flows" through the insulating material, allowing Ampères Law to remain valid and correctly describe the resulting magnetic field, despite the absence of a conventional current. It's this displacement current that effectively "closes" the current loop when a circuit with a capacitor is considered, which is essential for the continuity of electric and magnetic fields as described by Maxwell's Equations. This is quite relevant for interconnects since they have capacitance; the signal conductor and the return conductor are separated by a dielectric, forming a capacitor. Therefore, there will be displacement currents involved. We will soon see the issues those will bring. Maxwell's equations are the foundation of classical electrodynamics, classical optics, and electric circuits like interconnects. These four equations describe how the electric and magnetic fields are generated and altered by each other and by charges and currents. Maxwell's equations, for a medium that is not free space (i.e., a medium that may have different permittivity $\large\epsilon$, permeability $\large \mu$, and possibly conductivity $\large \sigma$) are as follows: Gauss Law for Electricity: $\large \nabla \cdot \mathbf{D} = \rho$ Here, $\mathbf{D}$ is again the electric displacement field, which relates to the electric field $E$ as $\, D = \epsilon\, E$, and $\rho$ is the free charge density. In materials with conductivity$\large\text{\ σ}$, the current density $\large J$ is related to the electric field by Ohm's Law: $J = \large \sigma\mathbf{E}$ For non-magnetic materials $\large \mu = \mu_0$, where $\large \mu_{0}$ is the permeability of free space, the relationship between the magnetic flux density and the magnetic field intensity $\mathbf{H}$ is simply: $\large \mathbf{B} = \mu \mathbf{H}$ In general, in materials with a non-linear response, the relationship between $\mathbf{D}$ and $\mathbf{E}$, and between $\mathbf{B}$ and $\mathbf{H}$, can be more complex and may not be strictly proportional. Additionally, in anisotropic materials, these relationships can be direction-dependent and described by tensors instead of simple scalar multiplication. ==In essence, Maxwell's equations depict that a changing magnetic field produces a changing electric field, and this changing electric field produces another changing magnetic field.== Thus, the cycle continues, and an electromagnetic wave is self-sustained as it propagates along the medium. The thing is, a wave in an interconnect is not only capable of traveling in one way (that is, from source to load), but also can make it back from load to source, and there are quite substantial issues associated with waves traveling back in interconnects when the frequencies involved are high enough that we shall discuss in due time. ==As an appetizer, let's just say that a reflected wave may (and will) interact with waves traveling forward and thus affect the overall signal quality—which ultimately is the combination of all these waves—and induce errors in our data.== The principal practical problem with Maxwell's equations, however, is not their shaky physical basis, but the sheer difficulty of the mathematics that results from trying to use them: they are incapable of analytical solutions in most situations of practical interest unless it is possible to make some drastically simplifying assumptions. The alternative (more soundly based) quantum mechanical approach is usually even more intractable, however. So the rule is to use Maxwell's equations wherever you can, and quantum mechanics only where you must. Even so, because Maxwell's equations rarely lead to easy mathematics, in the past very major simplifying assumptions often had to be made to achieve acceptable analytical solutions, and this was hardly satisfactory. With the progressive fall in computing costs, this is no longer the problem it was, because solutions can be obtained using numerical methods, particularly the finite element technique. Most people who use Maxwell's equations to solve actual electromagnetic problems consequently adopt a numerical rather than an analytical approach. After Maxwell's early death, Albert Michelson and Edward Morley devised experiments that showed that the ether Maxwell had assumed did not exist, thus demolishing the basis of his theories. However, although the physical ideas Maxwell used to arrive at his equations were quite wrong, the equations remained a good fit for observations (in all but a very few cases). They continued to give the right answers, even though the path to them was discredited, and they remain very widely used to this day. Many textbooks avoid mentioning their inadequate physical foundations. > [!Note] > Maxwell's work led to the conclusion that light consisted of electromagnetic waves, which was in line with the scientific beliefs of his time and seemed to have been confirmed experimentally. Now we know that the carrier particles of light (therefore, of electromagnetic waves) are photons. Are photons still involved when we launch an electromagnetic wavefront across a cable? > When an electromagnetic wave travels through a copper cable or PCB (Printed Circuit Board) traces, the primary particles involved are still photons. However, in these materials, there is also an interaction with electrons. > In a copper cable or PCB, the conductive material (such as copper) contains free electrons that can move relatively freely within the material. When an electromagnetic wave passes through these materials, the electric and magnetic fields associated with the wave interact with these free electrons. As the wave encounters the conductive material, the electric field component of the wave exerts a force on the free electrons, causing them to move back and forth within the material. This movement of electrons contributes to the transmission of the electromagnetic wave through the material. > So, while photons are still the carriers of the electromagnetic wave, the interaction with the free electrons in the conductive material plays an important role in how the wave propagates through a copper cable or PCB traces. > Although transmission lines are typically studied at a macroscopic level, their behavior ultimately emerges from the underlying quantum nature of electromagnetic fields and interactions between charged particles. ### How an Electromagnetic Wave Propagates in an Interconnect Electromagnetic wave propagation in an interconnect involves the following steps: 1. Field Generation: - ==When a time-varying voltage and current are applied to the interconnect, oscillating charges in the conductor produce oscillating electric fields between the conductor and the return plane.== - The oscillating currents create magnetic fields encircling the conductor according to Ampère’s law. 2. Field Distribution: - The electric field lines primarily stretch between the conductor and the return plane, with some fringing into the surrounding air. - The magnetic field forms loops around the current in the strip, both above the conductor and within the substrate. 3. Guidance by the interconnect: - The wave is guided along the interconnect due to the boundary conditions imposed by the conducting surfaces and the dielectric substrate. - The substrate concentrates the fields and increases effective capacitance, while the return plane provides a return path for currents, completing the transmission line circuit. 4. Energy Flow: - The energy propagates along the interconnect in the form of electromagnetic waves, carried by the Poynting vector $\mathbf{P} = \mathbf{E} \times \mathbf{H}$. - The majority of the energy is confined to the substrate, but some leaks into the surrounding air, affecting propagation characteristics. ### Interconnects in Terms of Voltages and Currents With all this, then it's perfectly accurate to think of transmission lines as waveguides where high-speed data signals manifest as electromagnetic waves propagating along the line. A "square" wave is nothing but pulses of electric and magnetic fields propagating from sources to loads. Interconnects are like a rope, and the signals are created by us whipping the rope accordingly. Still, it is of course possible to derive equations for the interconnect that model the distributed inductance, capacitance, and resistance and model interconnects from a spatial voltage and currents perspective. Charges are the entities that connect everything together: the wave concepts with voltages and currents. > [!info] > Voltage, also known as electric potential difference, is a measure of the work needed to move a unit charge between two points in an electric field. In practical terms, voltage "pushes" charges through a conductor, enabling the flow of electric current. >[!info] > Current is the rate at which electric charge flows through a conductor or a circuit. It quantifies the movement of charge carriers (typically electrons in a metal conductor) and is a fundamental concept in electricity. Thus, a set of transmission line equations—called the telegrapher's equations—is devised. The telegrapher's equations show the relationship between the time rate of change of the voltage and current and their spatial rate of change along the line. The transmission line is characterized by its per-unit-length parameters: resistance (R), inductance (L), conductance (G), and capacitance (C). $\large {\frac{\partial V\left( x,t \right)}{\partial x} = - L\frac{\partial I\left( x,t \right)}{\partial t} - RI\left( x,t \right) }{\frac{\partial I\left( x,t \right)}{\partial x} = - C\frac{\partial V\left( x,t \right)}{\partial t} - GV\left( x,t \right)}$ Where: $V\left( x,t \right)$ is the voltage as a function of position ($x$) along the transmission line and time $t$, $I\left( x,t \right)$ is the current as a function of position ($x$) along the transmission line and time $t$. $R$ is the resistance per unit length. $L$ is the inductance per unit length. ${G}$ is the conductance per unit length of the dielectric material separating the conductors. $C$ is the capacitance per unit length. These are called telegrapher's equation because the first time this was analyzed in depth, it was done by Oliver Heaviside and William Thompson for transatlantic telegraphic cables in the late 1850s. Back in the day, the laying of the intercontinental telegraph cable represented a major technological challenge. The early attempts to send messages across the ocean were plagued by slow and distorted signals. The culprit was the lack of understanding of how electrical signals behaved over long distances under the ocean. William Thomson was already involved in the project and had provided much-needed scientific advice during the design and laying of the cable. He realized that the cable acted like a long capacitor, with resistance and capacitance affecting the signal, causing it to become weaker and more spread out over distance. Oliver Heaviside, a self-taught electrical engineer, later applied his knowledge of James Clerk Maxwell's newly formulated theories of electromagnetism to the problem. Heaviside developed the telegrapher's equations, which provided a framework to understand how signals would degrade as they traveled. Heaviside proposed adding inductance to the cable to reduce signal distortion, a method known as "loading". Although initially his ideas were ignored because they went against established beliefs and Heaviside lacked formal recognition, they were eventually proven correct. Thomson, with his scientific stature, also helped promote the understanding of the cable's physics. The collaboration between Thomson and Heaviside's theoretical work led to significant improvements in cable design and signal quality. The telegrapher's equations became a fundamental tool for designing and understanding telecommunication lines, paving the way for reliable long-distance electrical communication. > [!important] > The transmission line equations are a special case of Maxwell’s curl equations in one dimension. ### The physical meaning of Inductance, Capacitance, and Resistance How come we start talking of things like inductance, capacitance, and resistance when all we have are waves traveling from here to there? These are merely physical effects that are given a specific name but remain perfectly consistent with the underlying wave-like nature of signals. #### Inductance We seem to struggle to articulate what inductance is, and it's not our fault. It's the way we're taught. Most textbooks teach us that inductance is a property of an electrical conductor or circuit that causes it "to oppose a change in the current flowing through it", and that it is defined as the ratio of the induced electromotive force (emf) in the conductor or circuit to the rate of change of current through it. Textbooks tend to solemnly go like this: Inductance, denoted by the symbol $L$, is measured in Henrys (H) and is given by the equation: $L = \LARGE \frac{\text{NΦ}}{I}$where: $N$ is the number of turns in the coil, $\Phi$ is the magnetic flux through the circuit in Webers (Wb), and $I$ is the current in Amperes (A). The typical textbook definition seems to revolve around currents, fluxes, and some "turns in the coil". Is inductance then only present when there are coils present? Were the transatlantic cables of Heaviside and Thomson coils, then? In fact, you do not necessarily need a coil to have inductance. A coaxial cable, a planar PCB trace, a cable between two racks in a data center, or a cable between continents; they all can show inductance. It's more accurate to observe that coils (or more specifically, loops) can **increase** inductance, and we will see a bit further ahead how these loops can be problematic for the quality of the signals we launch in our channels. Let's try to tackle inductance using a more physical intuition than formulas. But first, a quick disambiguation between magnetic flux, magnetic field strength, and magnetic field flux density. These terms are related but describe slightly distinct concepts in the study of electromagnetism: - Magnetic Flux $\large \left( \Phi \right)$: it refers to the total magnetic field which passes through a given area ($A$). - The unit of magnetic flux is the Weber (Wb). - The formula to calculate magnetic flux is: $\large \Phi = B \cdot A \cdot \cos\left( \theta \right)$ - Where $B$ is the magnetic flux density, $A$ is the area through which the field lines pass, and $\theta$ is the angle between the magnetic field lines and the perpendicular to the surface $A$. - Magnetic Flux Density ($B$): it represents the amount of magnetic flux through a unit area taken perpendicular to the direction of the magnetic flux. It represents how dense the field lines are at a given point in space. - The unit of magnetic flux density is the tesla ($T$), which is equivalent to webers per square meter (Wb/m²). - Magnetic flux density is often what people mean when they talk colloquially about "magnetic field" because it combines both the field strength and how the medium interacts with the magnetic field (permeability). - Magnetic Field Strength ($H$): Also called magnetic field intensity, it is a measure of the strength of the magnetizing field coming from a magnet or a current-carrying conductor. - The unit of magnetic field strength is amperes per meter (A/m). - In simple terms, it is how strong a magnetizing source is, without considering the medium in which it exists. To summarize: - Magnetic flux corresponds to the number of magnetic field lines passing through an area. The more lines pass through, the greater the flux. Magnetic field lines are imaginary lines used to represent the direction and strength of a magnetic field. - Magnetic flux density refers to how dense the magnetic field lines are per unit area. If the field lines are densely packed in a region, the magnetic flux density is high. - Magnetic field strength relates to the ability of the field to induce a magnetizing force in a material. The closer the field lines are to each other, the stronger the magnetic field strength. To illustrate inductance, we will use a simple experiment. Let's imagine a wire, a simple wire. Let's picture we pierce a piece of paper with this wire, and we make a 1-amp current flow through that wire. From Ampère's Law (with Maxwell's contribution), we know magnetic field lines will be present around the wire as the current flows. Now, imagine we sprinkle some iron fillings on that piece of paper, so we will see how the iron fillings align in the direction of the magnetic field. We can see the magnetic field lines around the current in that wire, the one amp of current in that wire. When there is current flowing through a conductor, we will always have these rings of magnetic field lines around it. Those rings of magnetic field lines, manifested as circular concentric rings, also have a direction of circulation. The direction of circulation is according to the right-hand rule (see figure below). So, to define the direction of circulation of field lines, we take the thumb of our right hand and point it in the direction of the current flow, with our fingers now curling in the direction of circulation of the magnetic field lines. Looking at it from above, the lines would be going in the counterclockwise direction.  > [!Figure] > *Right-hand rule and magnetic field lines for a wire carrying a current* Any wire with current flowing through it will have rings of magnetic field lines. If we double the current, the number of field lines will also double. The number of field lines is directly proportional to the current. If we considered a shorter portion of our test wire and counted the field lines, we would count fewer lines. So, the length over which we are counting the rings of field lines is going to influence the number of rings of lines that we see. Another physical property that influences the number of rings of field lines we see around the wire is its diameter. Using a wider diameter conductor, for the same current, we will see fewer field lines because there are fewer lines on the outside as some will now be sheltered on the inside. The larger the diameter, the fewer number of rings of field lines we are going to see around it. But the experiment we have been using thus far (the wire piercing through a sheet of paper with one amp of current flowing through it), is incomplete. ==Currents flow in loops. Somewhere, there must be a return path for this wire, otherwise there would be no electrical circuit possible. And by definition, the direction of the current and the return path is the opposite. So, we will also get the same field lines, and the same rings of magnetic fields around the return path, and some of those rings of field lines are so big and floppy that will encircle our signal conductor.== If we bring these two conductors—the signal, and the return path—closer together, the number of rings of field lines from the return path that will encircle the signal path will increase. However, the direction of circulation of the rings of field lines in the return path compared to the signal path will be opposite. If we tried to compute the total number of field lines around the signal path, it would need to consider its own rings of field lines minus the rings of field lines from the return path. Those lines that originate from the current flowing through the signal conductor, are called self-field lines. Now, the field lines that are so big and floppy, originating from the returning current in the return path that goes around the signal path, we will call those the **mutual field lines**. Therefore, when we look at the total number of field lines around the signal path, we must compute the self-field lines minus the mutual field lines. As interconnect designers, if we wanted to modify the number of self-field lines in the wire, we would have two possible "knobs" to turn. One is the length. A shorter conductor will have fewer self-field lines around it. And the other one will be the diameter. To have fewer self-field lines, we can use a wider diameter conductor. And of course, we still have the quintessential "know": the current. Half the current will give us half the number of self-field lines. If the current through a conductor doubles, the number of field line rings doubles, but the ratio stays the same. This ratio is completely independent of how much current is going through the conductor. A conductor has the same inductance if 0 Amps are flowing through it or 100 Amps. Yes, the number of field line rings changes, but the ratio doesn’t, and inductance is the ratio. In essence, inductance is not really about how many field lines we count, but about how efficient a conductor is in generating rings of field lines. Inductance is, physically speaking, about how many of those rings of field lines we get for a given amount of current, for example, per amp of current. If the conductor is efficient, meaning that the conductor is good at generating rings of field lines per amp of current, then it's a high inductance conductor. As we said, if we doubled the current through the wire, the number of rings of field lines would double. But the ratio shall stay the same. ==This ratio—how many rings of field lines per amp of current—is a measure of efficiency. A large ratio will indicate that a small current will give a large amount of field lines. Conversely, a small ratio will indicate we shall put a high current through the conductor to get a small amount of field lines out of it. That is the fundamental definition of inductance.== The unit that is used to define how many rings of field lines are generated per amp of current is Weber per amp, which we call a Henry of inductance. If the current through a conductor doubles, the number of field line rings doubles, but the ratio stays the same. This ratio is completely independent of how much current is going through the conductor. A conductor has the same inductance if 0 Amps are flowing through it or 100 Amps. Yes, the number of field line rings changes, but the ratio doesn’t, and inductance is the ratio. This means that inductance is really related to the geometry of the conductors. The only thing that influences inductance is the distribution of the conductors and, in the case of ferromagnetic metals, their permeability. Inductance is a measure of the efficiency of the conductors to create magnetic field line rings. A conductor that is not very efficient at generating magnetic field line rings will have low inductance. A conductor has an efficiency whether or not it has current through it. The amount of current in the conductor does not in any way affect its efficiency. Inductance is only about a conductor’s geometry. What makes the inductance concept a bit complicated and confusing is having to keep track of how much of the current loop we are counting the field line rings around and which other currents are present, creating field line rings. This gives rise to many different "kinds" or subtypes of inductance. To keep track of the source of the magnetic-field line rings, we will use the terms self-inductance and mutual inductance. To keep track of how much of the current loop around which we are counting field line rings, we will use the terms loop inductance and partial inductance. Finally, when referring to the magnetic-field line rings around just a section of an interconnect, while the current is flowing through the entire loop, we will use the terms total inductance, net inductance, and effective inductance. These last three terms are used interchangeably in the industry. Using the term 'inductance' alone is ambiguous. We must develop the discipline to always use the qualifier of the exact type of inductance to which we are referring. The most common source of confusion about inductance arises from mixing up the various types of inductance. ##### Self-Inductance and Mutual Inductance If the only current that existed in the universe were the current in a single wire, the number of field line rings around it would be easy to count. However, when there are other currents nearby, their magnetic field line rings can encircle multiple currents. #### Capacitance Capacitance is a physical measure of a system's ability to store electrical energy in an electric field. How is energy stored in electric fields? Energy is stored in an electric field due to the work done to move charge carriers against the force exerted by the field. When a potential difference (voltage) is applied across two conductive plates separated by a dielectric (i.e., a capacitor), an electric field is established between the plates. This field exerts a force on charge carriers (like electrons), pulling them toward one plate and pushing them away from the other. As electrons accumulate on one plate, they are removed from the other, leaving behind positive charges, which effectively create a negative plate and a positive plate. To move these charges against the electric field (which naturally repels like charges and attracts unlike charges), work must be done by an external power source, like a battery. This work is equivalent to the energy required to separate positive and negative charges, overcoming the attractive force between them. Once the charges are separated, this energy is stored in the system. The energy stored in an electric field $\left( E \right)$ within a capacitor can be mathematically expressed as: $E = \large\frac{1}{2}CV^{2}$ where $C$ is the capacitance of the capacitor and $\text{\ }V$ is the voltage across it. This equation shows that the energy is proportional to the square of the voltage; doubling the voltage increases the energy by a factor of four. It also depends linearly on the capacitance; double the capacitance and you will double the energy stored for a given voltage. On a microscopic scale, the electric field influences the alignment of the electric dipoles within the dielectric material and stretches the bonds, which also contributes to energy storage. This is because the field aligns the dipoles so that their positive and negative charges are in line with the field, resulting in a more energetically stable configuration that further stores energy (we discuss this effect again when we discuss [[Physical Layer#Losses|losses]] in interconnects further ahead). The energy stored is readily recoverable and can be used to do work in a circuit, manifesting as a flow of electrons when the capacitor is connected to a load. The physical quantity of capacitance quantifies how much electric charge is stored per unit of voltage; a ratio expressed in farads (F). It reflects how well a capacitor can hold charge at a given voltage. The capacitance is directly proportional to the surface area of the plates and inversely proportional to the distance between them. A larger plate area permits more charge to be stored, and a smaller separation allows the charges to feel each other's presence more strongly, thus enhancing the capacitance. The dielectric material between the plates also affects capacitance. Every material has a characteristic called the dielectric constant, which measures the material's ability to support an electric field. A higher dielectric constant means the material can insulate better, allowing the plates to hold more charge at a specific voltage, increasing the capacitance. #### Resistance Resistance in electrical circuits is a measure of the opposition to the flow of electric current. It's a physical property resulting from the interactions between the moving charges (usually electrons) and the atoms within a conductive material. When an electric potential (voltage) is applied across a conductor, it creates an electric field that pushes the free electrons in the conductor, causing them to drift toward the positive terminal. However, as these electrons move, they collide with the atoms in the material. Each collision causes the electrons to lose some of their energy, which is transferred to the atoms, increasing their vibrational energy and thus generating heat. The physical basis of resistance is thus largely due to these electron-atom collisions. The likelihood and impact of such collisions are influenced by several factors such as the material (different materials have different numbers of free electrons and atom densities and materials with more free electrons—like metals—generally have lower resistance, while those with fewer free electrons—like ceramics—have higher resistance. Also, as temperature increases, atoms vibrate more vigorously, leading to an increase in the number of collisions and hence increased resistance. The resistance of a material also depends on its size and shape. Longer conductors have more resistance because electrons have a greater distance over which to collide with atoms. Conversely, wider conductors have less resistance because there is more area for the electrons to flow through, reducing the number of collisions per unit area. The arrangement of atoms in a solid affects how easily electrons can pass. Materials with a regular crystal lattice structure generally have lower resistance than those with defects or disordered structures. Resistance is given by the equation $R = \large \rho\frac{L}{A}$, where $\rho$ (rho) is the resistivity of the material (a property that quantifies how strongly the material opposes current), ${L}$ is the length of the conductor, and ${A}$ is the cross-sectional area. Resistivity itself is a property determined by the material's electronic structure and temperature. --- ==It should be clear by now that there are essentially two ways of viewing interconnects, and that both can perfectly coexist, depending on what we are trying to analyze or design: the field way (signals as propagating magnetic and electric fields), and the circuit approximation way (signals as voltages and currents coupled through capacitance and inductance)== > [!Note] A quantum interpretation > German physicist Heinrich Hertz^[https://en.wikipedia.org/wiki/Heinrich_Hertz] was among the first to experiment with the generation of radio waves by creating high-voltage sparks between two conductors, pioneering the investigations of electromagnetics and propagation. In reality, there were vast numbers of radio waves in the universe long before Hertz performed his famous experiments. Electromagnetic waves are generated naturally whenever electric charges are accelerated or decelerated. All hot objects, in which charged particles are in rapid random motion, radiate electromagnetic energy in various frequencies. The stars are potent sources of electromagnetic energy, which is the basis of radio astronomy. On our planet, atmospheric events such as lightning strikes produce showers of radio energy, noticeable as the background crashes and crackles heard on broadcast receivers during thunderstorms. In most of these cases of natural generation, the radio energy is incoherent, characterized by a jumble of photons of disparate energies. The same is true of many human-made sources of electromagnetic disturbances, such as electrical machinery. We now know that the ether, assumed by Maxwell and Hertz, does not exist. The waves Hertz thought he had discovered were not at all what he supposed either. What he actually generated was a stream of radio quanta, identical with the photons of light except for their energy, and small enough to have wave-like properties. > Particles can perfectly well move through empty space so the ether is irrelevant to quantum theory, and it is unnecessary to make any implausible assumptions about forces acting at a distance. The physical significance of the electromagnetic wave is that it tells us how likely we are to find a radio quantum because the square of the wave amplitude (its power level) is proportional to the probability of finding a quantum near the location concerned, and the Poynting vector $P = E \times H$ just gives us the rate of flow of quanta at the point where it is measured. ### Instantaneous Impedance When discussing signals as traveling waves, the concept of instantaneous impedance is very important. Instantaneous impedance in the context of a propagating wave in an interconnect is the ratio of the instantaneous voltage to the instantaneous current at a particular point on the line at a given moment in time. Mathematically, it's defined as: $\large Z\left( t \right) = \frac{V\left( t \right)}{I\left( t \right)}$ where $Z\left(t\right)$ is the instantaneous impedance, $V\left( t \right)$ is the instantaneous voltage, and $I(t)$ is the instantaneous current. Essentially, the instantaneous current is given by the amount of capacitance one must "charge up" as the signal propagates through the line. For a transmission line in the steady state (after any transients have died out), and under the assumption that the line has uniform characteristics, this ratio remains constant and is equal to the characteristic impedance $Z_{0}$ of the line. The characteristic impedance is a property of the line determined by its physical construction (the geometry and materials of the conductors and insulating medium) and is typically frequency-independent for a lossless line. In a real-world scenario, transmission lines are not uniform and present losses. At any instant in time, if there are reflections or non-uniformities, the instantaneous impedance will vary along the length of the line. In a perfectly matched transmission line, the instantaneous impedance at every point along the line and at every moment in time would be equal to the characteristic impedance. ### Transmission Lines and Characteristic Impedance of Interconnects In a uniform transmission line, the signal encounters a consistent instantaneous impedance irrespective of the line's length, whether it spans mere inches on a circuit board or extends over kilometers in a cable. This consistent impedance is referred to as the characteristic impedance, denoted by $Z_{0}$, symbolizing that it is not the immediate impedance but a unique property intrinsic to the transmission line. This impedance is a critical parameter as it dictates the response of a signal traversing the line. Additionally, the transmission line possesses a second relevant property: the time delay. This is the duration required for a signal to traverse from one end of the line to the other and is influenced by the lines length and the signal velocity, the latter of which is determined by the dielectric properties of the material constituting the interconnect. The characteristic impedance and the time delay are defining features of every interconnect, essential to understanding and modeling such elements within electrical circuits. ==The 'transmission line model' is thus a hybrid tool in circuit theory that acts as a bridge between conventional voltage-current perspectives and electromagnetic field considerations.== To exemplify, consider a signal encountering a transmission line with a return path; the immediate impedance it meets is the line's characteristic impedance. This impedance will persist uniformly along the transmission line until the signal emerges at the other end. The impedance at the exit, however, is contingent on the external circuitry attached to the line, which may affect the signal's subsequent behavior. In calculating the characteristic impedance, one encounters complexities due to fringe fields and spatial distribution of the fields, which are influenced by the capacitance per unit length and the material properties. These factors make it challenging to determine impedance with basic calculations, needing some software tools. By inputting the relevant dimensions and material characteristics into the tool, one can simulate the effects that varying the line width will cause on the characteristic impedance, aiding in design decisions to meet specific impedance targets. These tools are indispensable for accounting for the complex effects of conductor geometry and material distribution on the transmission line's characteristic impedance. The equation for the characteristic impedance in terms of the line's inductance per unit length $L$ and capacitance per unit length $C$ is: $\large Z_{0} = \sqrt{\frac{L}{C}}$ How is this formula obtained? To derive the characteristic impedance $Z_0$, we will assume a lossless transmission. A lossless line is an idealization where the resistance per unit length ${R}$ and the conductance of the dielectric per unit length $G$ are both assumed to be zero. This simplification allows us to focus on the line's inductance $L$ and capacitance $C$ per unit length. As we saw, the behavior of electrical signals on a transmission line can be described by the telegrapher's equations, which are in turn derived from Kirchhoff's voltage and current laws (KVL and KCL). For a differential segment of the transmission line: - KVL leads to the voltage equation: $\large \frac{\partial V}{\partial x} = -L \frac{\partial I}{\partial t}$ This equation states that the change in voltage $V$ along the line $\partial V/\partial x$ is related to the change in the current $I$ over time $\partial I/\partial t$ multiplied by the inductance per unit length $L$. - KCL leads to the current equation: $\large \frac{\partial I}{\partial x} = -C \frac{\partial V}{\partial t}$ This equation shows that the change in current along the line $\partial I/\partial x$ is related to the change in voltage over time $\partial V/\partial t$ multiplied by the capacitance per unit length $C$. By taking the derivative with respect to $x$ of the first equation and substituting the second equation into it, we can derive a wave equation for voltage. Similarly, we can derive a wave equation for current by taking the derivative with respect to $x$ of the second equation and substituting the first into it. - Differentiating the voltage equation with respect to $x$ and substituting the current equation yields: $\large \frac{\partial^2 V}{\partial x^2} = LC \frac{\partial^2 V}{\partial t^2}$ - Similarly, differentiating the current equation with respect to \(x\) and substituting the voltage equation yields: $\large \frac{\partial^2 I}{\partial x^2} = LC \frac{\partial^2 I}{\partial t^2}$ These are wave equations that describe how voltage and current waves propagate along the transmission line with a phase velocity $v = 1/\sqrt{LC}$. The characteristic impedance of the transmission line is defined as the ratio of the voltage to the current for a forward-traveling wave, which means $V = Z_0I$. Given a forward-traveling wave, we can express $V$ and $I$ as functions of $x$ and $t$, acknowledging that these quantities vary in space and time as the wave propagates along the line. The characteristic impedance is derived by solving the differential equations above for $V$ and $I$ under the assumption of a forward-traveling wave (or considering the relationship between the voltage and current in such a wave). The impedance is not dependent on the wave's shape or speed but on the medium's properties through which it travels—namely, the transmission line's inductance and capacitance per unit length, which yields the formula we introduced before, which states that the characteristic impedance is determined by the square root of the ratio of the line's inductance per unit length to its capacitance per unit length. For an interconnect like a microstrip (see figure far below), the calculation of the characteristic impedance is governed by the geometry of the microstrip, and the properties of the materials used. A microstrip consists of a flat conductor strip separated by a dielectric layer from a large ground plane. The characteristic impedance ${Z_0}$ of a microstrip line is primarily a function of the width of the strip (W), the thickness of the dielectric layer (H), the dielectric constant of the substrate material $\large \varepsilon_{r}$, and to a lesser extent, the thickness of the strip (T), which is usually much smaller than the width and can often be neglected in the calculation. To calculate the characteristic impedance, the following steps are generally taken: - The width-to-height ratio (W/H) of the microstrip is assessed. - The effective dielectric constant $\large \varepsilon_{\text{eff}}$ is calculated because the electromagnetic field in a microstrip line is partly in the dielectric and partly in the air, which affects the velocity of propagation and the impedance. - An appropriate formula is used based on the W/H ratio. There are several empirical formulas available to calculate the impedance, and the most common ones are derived from conformal mapping techniques or full-wave electromagnetic field solvers. The formulas differ for cases where W/H is less than or greater than 1. For example, a widely used empirical formula when W/H is less than 1 is given by: $\large Z_{0} = \frac{60}{\sqrt{\epsilon_{\text{eff}}}}\ln\left( \frac{8H}{W} + \frac{0.25W}{H} \right)$ And when W/H is greater than 1, another empirical formula is: $\large Z_{0} = \frac{120\pi}{\sqrt{\epsilon_{\text{eff}}}}\left( \frac{W}{H} + 1.393 + 0.667\ln\left( \frac{W}{H} + 1.444 \right) \right)^{- 1}$ These formulas assume that the microstrip is infinitely long and that the edges of the strip conductor are straight and parallel. In practice, these calculations are often aided by the use of solvers, which can consider more complex factors for more precise impedance calculations. The correct impedance calculation in a microstrip is essential for ensuring the matching of the microstrip line to other circuit elements, minimizing signal reflections, and reducing loss. Inaccurate impedance can lead to signal degradation and power loss, so careful design and consideration of the characteristic impedance are important in microstrip and other high-speed circuits.  > [!Figure] > *A microstrip with one conductor on top, one on the bottom, and a dielectric insulator in between* > [!info] > In waveguides and transmission lines, there are different ways the electromagnetic waves can propagate through the medium. The three different modes refer to how the electric (E) and magnetic (H) fields are oriented relative to the direction of propagation: > - TEM is propagation through a pair of conductors with both the electric and magnetic fields perpendicular to the direction of travel. A cable has the same field structure regardless of the frequency. > - TE and TM are modes where only the electric or magnetic fields are "transverse", having no component in the direction of travel. There is no second conductor. > > A cable operates all the way down to DC because you have conductors that facilitate actual return currents and frequency independent field structure. A waveguide has a cutoff frequency because it depends on the ability to generate constructive self interference as the wave reflects through the structure. ### Digital Signals, Symbols, Data Rate, Bandwidth, Nyquist Frequency and Unit Intervals All this discussion about electromagnetic waves, currents, voltages and whatnot comes together when we discuss what we use interconnects for. We always use interconnects and channels to transmit signals. That is, we take advantage of physical phenomena to convey information across a channel, be it a coax, PCB tracks or free space. A signal, in this context, is an arbitrarily chosen variation of a physical effect in a channel that represents *something*. Wow that wasn't very clear, right? Hopefully the paragraphs below will illustrate what this somewhat obscure sentence means. In digital systems, signals swing between certain voltage values during specific time intervals. It is very relevant for digital communication that these details (time durations and voltage levels) are agreed between transmitters and receivers. If there were no agreement, the receivers would not be able to reconstruct the bitstreams because a. They would not know what voltage thresholds represent which logic values b. They would not know where a data bit starts and where it ends. High-speed, serial digital communication requires that transmitters and receivers work on the same contract when it comes to signal specs.  > [!Figure] > *A digital signal* Receivers reconstruct bitstreams by means of probing—sampling—the incoming signals at specific times and deciding what value the incoming symbol means. And now we have just used a new term: symbol. What is a *symbol*? A symbol is anything that represents something. Ok, that was not the clearest explanation ever. Let me clarify. In terms of digital signals, a symbol is a voltage that represents a digital value. The simplest case is an on/off signal swinging between a certain voltage (say, 2 volts) and 0 volts. We have, as designers, the power to define how symbols will map into value. In our experiment, we decree that a 2-volt symbol will represent a value of 1 in the digital domain, whereas 0 volts will represent a digital 0. Therefore, a receiver prepared to work according to this contract will decode a digital 1 every time it sees 2 volts coming in and will decode it as a digital zero when there is no voltage. In this case, one symbol maps to one bit, which also means that the data rate will be the same as the symbol rate. Symbol rate, or the amount of time a signal changes states per second, is quantified in a unit called baud. Data rate is the number of bits per unit of time transferred through an interconnect. Note that other parameters of a signal could be altered to create symbols, for instance, phase or frequency. Equivalently, one phase value could mean one bit (a case called binary phase keying) or a phase value could mean more bits. Note that digital signals in serial links might choose more complex schemes than the ones we used. For instance, PAM (pulse amplitude modulation) is a scheme where the signal uses a higher number of amplitude levels to represent digital data (see figure below). Each amplitude level in the train represents a data symbol, and the amplitude of the pulse corresponds to a specific binary value. For instance, in PAM4 there are four amplitude levels: each level represents two bits. Therefore, in PAM4, the symbol rate (baud rate) is half the data rate, because for every symbol we can obtain two data bits. The figure below sums it up (see also note).  > [!Figure] > _NRZ versus PAM4 signaling schemes (note that the horizontal axis is purposely left out to avoid arbitrarily defining voltages)_  > [!Figure] > _PAM4 eye pattern. Credit: Ansys_ > [!note] > To keep up with the bandwidth demands of the industry, non-return-to-zero (NRZ) signaling has been increasingly replaced by pulse amplitude modulation level-4 (PAM4) signaling. To maintain the same naming convention, NRZ signaling is now referred to as PAM2. Both terms are acceptable. PAM2 has been widely used in various serial communication interfaces over the years due to its simplicity, robustness and lower cost to implement. The signal level remains constant during the bit interval, which helps in maintaining signal integrity with good margin. For decades it has been the workhorse for standards like the [[High-Speed Standard Serial Interfaces#PCI Express|PCIe]] and the [[High-Speed Standard Serial Interfaces#Ethernet|Ethernet]], but as bit rates surpassed 32 Gbps, PAM4 signaling has become the standard. PAM4 is used in high-speed data communication to effectively double the serial data rate without requiring an increase in channel bandwidth. It is commonly used in high-speed standards, such as 100 G, 200 G, and 400 G Ethernet. It has also been adopted for PCIe Gen 6 and future Gen 7 standard. But unlike PAM2, as we showed above PAM4 uses four distinct voltage levels to represent data. Figure below shows a comparison of (a) NRZ (PAM-2) encoding versus PAM-4 encoding and (b) respective eye diagrams ([source](https://www.signalintegrityjournal.com/blogs/12-fundamentals/post/3794-pam2-vs-pam4-signaling-simply-explained)): > > ![[Pasted image 20250109221443.png]] > > As shown in part (a) of the figure, each bit time, or unit interval (UI) of a PAM2 data channel, contains one symbol, which can represent either a logic zero or a logic one. In this case the bit rate is equal to the baud rate. In PAM4 signaling, one symbol from each of the PAM-2 data channels are encoded into one bit stream using the Gray coding algorithm. The result is four voltage levels, with two symbols transmitted per UI, effectively doubling the bit rate for the same baud rate. For instance, if the bit rate is 56 Gbps, the baud rate would be 28 GBaud. > The PAM4 eye diagram in part (b) of figure above shows three distinct eye openings, with on-third the voltage amplitude VA, compared to the single eye opening in PAM2. These levels are binary coded as 00, 01, 10, and 11. This difference in eye opening however, leads to a 9.6 dB reduction in signal to noise ratio. This means it’s more susceptible to noise, requiring more advanced signal processing and error correction. Fortunately, forward error correction coding is used to compensate. > The shift from NRZ (PAM2) to PAM4 signaling has enabled higher data rates while maintaining bandwidth efficiency, despite its increased complexity and noise sensitivity. As data needs continue to grow due to computing and AI demands, the adoption of PAM4 standard has paved the way for future PAM-level encoding schemes to address future bandwidth limitations, prolonging the life of copper interconnect. For a square digital signal, the fundamental frequency is called the Nyquist frequency. The Nyquist frequency is half the maximum data rate of the signal, given that each full period of the fundamental can represent two bits of information. This way, a data rate of 5 Gbps represents a 2.5 GHz fundamental. In any signal, the fundamental frequency and harmonics will occupy bandwidth as they are transmitted through a physical interconnect, and the bandwidth will be directly related to the "squareness" of the signal. A rule of thumb relates the bandwidth of the system (which is a function of the number of harmonics) to the rise time of the signal. The rise time of a digital signal is the time it takes for the signal to transition from a low (0) to a high (1) state (or vice versa), typically measured from the 10% to 90% levels of the transition. To achieve a sharp and clear rise time, the signal must contain a sufficient number of harmonics. If the bandwidth is too narrow (i.e., if it lacks higher harmonics), the rise time will be slower, leading to more rounded, less distinct transitions. ==As a rough rule of thumb, the rise time of a signal propagating down an FR4 transmission line will increase its rise time by about 10 psec/inch of travel.== A commonly cited rule of thumb is that the bandwidth of a system should be approximately the inverse of the rise time for a square wave to maintain its shape effectively. This can be expressed as: $\large \text{BW\ (Hz)} \approx \frac{0.35}{\text{Rise\ Time\ (seconds)}}$ Heuristic rules say we must usually strive for an interconnect bandwidth (BW) five times the Nyquist frequency of the bit rate. Five times Nyquist represents the fifth harmonic sinusoidal component of a Fourier series. An interconnect bandwidth up to the fifth harmonic preserves the integrity of the rise time down to 7 percent of the period (T) of the fundamental frequency. For example, if a digital signal has a rise time of 1 nanosecond (ns), the necessary bandwidth to maintain this rise time would be approximately 350 MHz. This relationship arises because a square wave (or a sharp rising and falling edge in a digital signal) is composed of a fundamental frequency and its odd harmonics. The faster the rise time, the higher the frequency of the harmonics needed to maintain that rise time. In essence, a sharp rise time means the signal has high-frequency components, and these high-frequency components are the higher harmonics of the signal. The following code snippet illustrates the contribution of harmonics for an NRZ square wave. ```python import numpy as np import matplotlib.pyplot as plt # Parameters for the square wave T = 1.0 # Period of the square wave fs = 1000 # Sampling frequency t = np.arange(-1.5*T, 1.5*T, 1/fs) # Time array # Generating the square wave (fundamental frequency) fundamental_freq = 1/T square_wave = np.sign(np.sin(2 * np.pi * fundamental_freq * t)) # Initialize the plot with a suitable size plt.figure(figsize=(15, 20)) # Plot the square wave plt.subplot(11, 1, 1) plt.plot(t, square_wave, label='Square Wave') plt.title('Cumulative Effect of Harmonics in Forming a Square Wave') plt.xlabel('Time [s]') plt.ylabel('Amplitude') plt.grid(True) plt.ylim(-1.5, 1.5) # Initialize the cumulative sum of harmonics cumulative_harmonics = np.zeros_like(t) # Add and plot the harmonics cumulatively for n in range(1, 11): harmonic_freq = n * fundamental_freq if n % 2 != 0: # Include only odd harmonics harmonic = (4/np.pi) * (1/n) * np.sin(2 * np.pi * harmonic_freq * t) cumulative_harmonics += harmonic # Plot the cumulative sum of harmonics plt.subplot(11, 1, n + 1) plt.plot(t, cumulative_harmonics, label=f'Up to {n}th Harmonic') plt.ylabel('Amplitude') plt.grid(True) plt.ylim(-1.5, 1.5) plt.xlabel('Time [s]') plt.tight_layout() plt.show() ``` Which yields:  > [!Figure] > _Effect of adding harmonics to a fundamental frequency (the topmost signal is the ideal signal)_ The following code snippet qualitatively illustrates the decrease in rise time as more harmonics are added to the fundamental (5 harmonics). Note that the measurement of the rise time is done with rudimentary thresholds, measuring the signal crossing from -0.9 to 0.9 in value. ```python import numpy as np import matplotlib.pyplot as plt # To analyze the rise time variation with the addition of harmonics, we will focus on the transition from -1 to 1 # in the square wave and measure how quickly this transition occurs as more harmonics are added. def measure_rise_time(signal, t, threshold=0.9): """Measure the rise time from -1 to 1 of the signal, defined as the time to go from -threshold to threshold.""" # Find the indices where the signal crosses -threshold and threshold start_idx = np.where(signal > -threshold)[0][0] end_idx = np.where(signal > threshold)[0][0] # Calculate the rise time rise_time = t[end_idx] - t[start_idx] return rise_time # Parameters for the square wave T = 1.0 # Period of the square wave fs = 1000 # Sampling frequency t = np.arange(-1.5*T, 1.5*T, 1/fs) # Time array # Generating the square wave (fundamental frequency) fundamental_freq = 1/T square_wave = np.sign(np.sin(2 * np.pi * fundamental_freq * t)) # Initialize the plot with a suitable size plt.figure(figsize=(15, 20)) # Plot the square wave plt.subplot(11, 1, 1) plt.plot(t, square_wave, label='Square Wave') plt.title('Cumulative Effect of Harmonics in Forming a Square Wave') plt.xlabel('Time [s]') plt.ylabel('Amplitude') plt.grid(True) plt.ylim(-1.5, 1.5) # Initialize the cumulative sum of harmonics cumulative_harmonics = np.zeros_like(t) # Initialize a list to store rise times rise_times = [] # Calculate rise times for the cumulative sum of harmonics for n in range(1, 11): harmonic_freq = n * fundamental_freq if n % 2 != 0: # Include only odd harmonics harmonic = (4/np.pi) * (1/n) * np.sin(2 * np.pi * harmonic_freq * t) cumulative_harmonics += harmonic rise_time = measure_rise_time(cumulative_harmonics, t) rise_times.append(rise_time) # Plotting rise times harmonic_numbers = list(range(1, 11, 2)) # Only odd harmonics plt.figure(figsize=(10, 6)) plt.plot(harmonic_numbers, rise_times, marker='o') plt.title('Variation of Rise Time with Number of Harmonics') plt.xlabel('Number of Harmonics') plt.ylabel('Rise Time (s)') plt.grid(True) plt.show() ```  > [!Figure] > _Rise time decrease with more harmonics (5 harmonics)_  > [!Figure] > _Rise time decrease with more harmonics (15 harmonics)_ To finalize this section, we will define the unit interval. The term "unit interval" refers to the time duration allocated for one symbol in a digital signal. The unit interval is essentially the inverse of the data rate. For instance, if a digital system transmits data at a rate of 1Gbps, the unit interval for this system would be 1 nanosecond (1ns). In other words, the unit interval is the time slot during which the value of a single symbol is transmitted. ### Timing Models ==There are fundamentally two ways of communicating two endpoints in a digital channel: synchronously and asynchronously.== In a synchronous system, both the sending and receiving entities share a common "heartbeat" of the communication, generally in the form of a clock signal. This clock signal—which can be explicit or implicit, as we will see below—coordinates the timing of data transmission and reception. In a synchronous system, the data is sent in a continuous stream, and each bit of data is read in time with the shared clock signal. The clock ensures that the sender and receiver are perfectly synchronized, allowing for an orderly exchange of data. In contrast, asynchronous communication does not rely on a shared clock signal. Instead, data is sent in chunks, with each chunk starting and ending with recognizable sequences to mark the boundaries of the chunk of data. In asynchronous communication, the sender and receiver must agree on the data format and the speed beforehand. Then, once the receiver recognizes the start sequence, it can sample in an open-loop manner (without feedback), trusting that the sender will toggle the data at the times they both agreed to. We will not discuss asynchronous communication much, as it does not scale well for high-speed communication. We will focus on synchronous communication. There are three basic timing models used for synchronous communication between two entities in a digital interconnect: system-synchronous, source-synchronous, and self-synchronous. Note that here we are not specifying if signals are differential or single-ended, as it would make the analysis even more complex. #### System-synchronous The system-synchronous timing approach is where all components of a digital system are synchronized to a single, global, common clock signal (see figures below). This method ensures that data signals are stable and valid at predictable times, aligning with the clock edges, typically the rising or falling edge. This predictability simplifies the design process as timing analysis becomes more straightforward, with a clear understanding of when data will be read or written. One of the main advantages of this approach is its simplicity in design and debugging. Since every component operates in sync with the clock, designers can easily predict and control the flow of data, reducing the likelihood of timing-related errors. It also facilitates the integration of different modules, as they all adhere to the same timing scheme. However, system-synchronous timing has its drawbacks. As the clock signals traverse through interconnects in PCBs and inside chip dies, delays and artifacts are added to the signal, introducing timing issues in the system.  > [!Figure] > *System-synchronous design. Credit: Xilinx.*  > [!Figure] > *Delays associated with system-synchronous timing model. Credit: Xilinx.* #### Source-synchronous Source-synchronous timing is an alternative approach to system-synchronous timing in digital design. In source-synchronous timing, the clock signal is generated by the same device that sends the data, and it is transmitted along with the data signals to the receiving device. This method is particularly effective in managing data transfer between two different components or systems that might not share a common clock source or operate at the same clock frequency.  > [!Figure] > *Source-synchronous system. Credit: Xilinx* The key advantage of source-synchronous timing is its ability to handle high data rates efficiently, especially in scenarios where data is being transferred over a distance that could introduce significant clock skew if a common clock were used. By sending the clock signal with the data, the receiving device can latch the data directly based on the accompanying clock, reducing the issues of clock skew and ensuring more accurate data capture. This is particularly useful in high-speed applications like DDR memory interfaces and high-speed serial communication, where maintaining data integrity at high transfer rates is of great importance.  > [!Figure] > *Delays associated with source-synchronous timing model. Credit: Xilinx* However, there are several challenges associated with source-synchronous design. The requirement to send a clock signal with the data can increase the number of required signal lines, complicating the physical layout of the system. There's also a need for careful alignment of the data and clock signals, as misalignment can lead to errors. This calls for more complex design considerations to ensure signal integrity, such as matched trace lengths for the clock and data lines (note that this issue is independent if the signals are single-ended or differential. Differential pairs will additionally show [[#Line-to-Line Skew|intra-pair skew]], which also needs special care). Another challenge is the need for a more sophisticated receiving mechanism, capable of adjusting to variations in the timing of the incoming clock signal. This can lead to increased design complexity and higher costs in the receiver circuitry. #### Self-synchronous In this approach, the clock signal is embedded within the data stream itself, rather than being transmitted separately as in traditional synchronous or source-synchronous systems. This technique is often used in serial communication protocols where signal integrity is critical. In a self-clocked system, special encoding schemes are used so that the clock information can be recovered from the data signal at the receiver end. One common method is to use a transition-based encoding, where the transitions (changes from 0 to 1 or 1 to 0) in the data stream are used to derive the timing information. Examples of such encoding schemes include Manchester encoding and [[Semiconductors#Field Programmable Gate Arrays (FPGA)#SerDes and High-Speed Transceivers#8b/10b Encoding/Decoding|8b10b encoding]].  > [!Figure] > *Self-synchronous system. Credit: Xilinx.*  > [!Figure] > *Manchester encoding, an example of clock-embedding* One classic example of self-synchronous coding is Manchester coding (see figure right above). In this type of signal, the high and low values of the signal are encoded in the transitions: a low-to-high transition is a 1, whereas a high-to-low transition is a zero (note that this is just a convention and there is also Manchester with the inverse polarity). Any entity decoding a Manchester bit stream would not only obtain the data but also stay in synch with the stream without an extra clock signal. Of course, the challenge would be to detect where the data stream starts. The advantage of embedding the clock within the data stream is the reduction in the number of physical connections required, as there is no need for a separate clock line. This can simplify the physical layout and reduce costs, especially in high-speed data transfer applications. Additionally, embedding the clock with the data helps to minimize issues related to clock skew and signal synchronization, as the timing information is inherently aligned with the data.  > [!Figure] > *Self-synchronous timing model. Credit: Xilinx.* The clock recovery process does not provide a common clock or send the clock with the data. Instead, a phase-locked loop (PLL) is used to synthesize a clock that matches the frequency of the clock that generates the incoming serial data stream (see figure above). A Phase Locked Loop (PLL) is an electronic circuit with the primary function of synchronizing an output oscillator signal with a reference signal in frequency and phase. It does this through a feedback system. The core components of a PLL include a phase detector, which compares the phase of the output signal with the reference signal; a low-pass filter, which smooths the output of the phase detector; and a voltage-controlled oscillator (VCO), which generates the output signal whose frequency is adjusted based on the input from the low-pass filter. By continuously adjusting the VCO, the PLL keeps the phases of the two signals aligned. However, this approach also has its downsides. The encoding and decoding processes can introduce complexity into the system. The receiver must have the circuitry for accurately extracting the clock signal from the incoming data stream. Moreover, because the clock information is derived from the data, the absence of data transitions for long periods can lead to a loss of synchronization. To prevent this, techniques like scrambling are employed, typically handled by the [[High-Speed Standard Serial Interfaces#PCS & PMA|PCS layer]] in standard high-speed interfaces. ## Signal Integrity Here's our fundamental challenge as digital systems designers: we want to send information as fast as possible from a transmitter to a receiver. Ideally, we want the information to be on the other side instantaneously. As per the [[The OSI Model|OSI model]], there are multiple ways of observing the information we send: from very high-level abstractions (represented by the higher layers of the model) to lower, less abstract levels closer to the physical medium. Eventually, all information sent through an electrical interconnect will necessarily be converted into a stream of bits (the *transfer syntax* [[Communication Between Heterogeneous Systems|as discussed]]) that will travel through a physical medium as wavefronts to be reconstructed at the other end. Needless to say, we want the information to arrive at the destination without any errors. No errors means that the interconnect must be perfectly transparent for the information traversing through it. There are three important features of a perfect interconnect: - The instantaneous impedance down the length matches the impedance of the environment in which it is embedded. - The losses through the interconnect are low, and most of the signal is transmitted; i.e.; no signal is lost in between. - There is negligible coupling to adjacent channels; that is, our interconnect works perfectly isolated from the known Universe. Because we know by now that information going through an interconnect is all about electromagnetic waves propagating down the channels, ==the fundamental problem we have to deal with as system designers is that no interconnect is perfect or transparent==. The idea that interconnects ideally transport our signals from transmitters to receivers without interacting with them, is naive and false. Our signals do interact with the interconnects, and interconnects interact with our signals. No interconnect is even close to ideal. ==More bluntly, interconnects screw up the signal, and there is little we can do about it.== Although we cannot prevent the interconnects from degrading our signals, what we can do is engineer our interconnects with a set of measures to minimize the effects they cause. And even if this was not enough, there are still things we can do at both ends (at the transmitter and receiver end) to improve signals in a way they are better prepared for realistic, imperfect channels. We will cover in this section the challenges associated with interconnects in digital systems and how, the higher the data rates, the worse the situation gets. >[!important] >When you route a signal and its return tightly together (twisted pair, trace over a solid plane, coax), you’re constraining the field loop, creating a shorter, tighter corridor for electric and magnetic fields. Separate them and you’re enlarging that loop in space, inviting trouble. So, with “field loop”, we mean the **closed, physical path of EM energy flow** set by the electric field from signal to return and the magnetic field around the current, which together ensure power and information can get from A to B and back. ### Reflections A wave will propagate smoothly as long as the medium is smooth. Otherwise, waves will scatter off and reflect. Just like when we throw a stone into a quiet pond, the waves generated from the stone transferring its kinetic energy to the medium (water) will scatter off from the point of impact. If one of those wavefronts finds an obstacle, for instance, a boat, the wave will interact with this object and scatter again in several directions; some of it will reflect right back. If there are still original waves from our stone on their way to the boat, they will interact with the reflected wave, creating an interference pattern in the process. Chances are that the reflected wave will also scatter again with something else and then head back to the boat until the wave energy wears out, and the pond will be quiet again. Waves reflect in a medium due to a change in the properties of the medium. This principle applies to various types of waves, including electromagnetic, sound waves, and mechanical waves, like waves on a string or in water, as in the example we just used above. > [!important] > I recommend watching the video below for a very didactic approach to waves and reflections (credit: AT&T). >  The concept of impedance is central to understanding why waves reflect. Impedance can be thought of as the resistance to wave propagation. When a wave travels from one medium to another, the difference in impedance between the two media determines how the wave behaves at the interface. Using mechanical systems to illustrate phenomena in electrical systems tends to be more intuitive; for waves traveling in mechanical systems (for instance, think of a rope), the concept of impedance is a measure of how much opposition a medium provides to the motion of the wave due to both inertia and resistance (akin to friction in mechanical movements). Mechanical impedance is defined as the ratio of the force applied to a system to the resulting velocity in that system. It's a complex quantity, consisting of both a real part (resistive) and an imaginary part (reactive). The resistive component is analogous to resistance in an electrical circuit. It represents the energy dissipated in the system, often due to friction or other forms of energy loss. The reactive component represents the energy stored in the system, either in kinetic form (due to mass/inertia) or potential form (due to elasticity). In electrical interconnects, impedance discontinuity is the sole reason for reflections. Unlike ponds, electrical interconnects are like hallways or tunnels for signals: waves cannot reflect in too many directions other than the direction of the propagation; in fact, if a wave in an electrical interconnect will reflect, it will not have any other choice than traveling right back to the source. Changes in the immediate impedance the signal sees as it propagates down these "hallways" will cause said reflections, and the reflected waves will create interference patterns with incident waves that will result in overvoltages or undervoltages depending on the conditions of the reflection, which may introduce errors in the decoding of the symbols represented by the signal at the receiver. Unsurprisingly, this is called Inter Symbol Interference (ISI) and it's a big problem in high-speed links as it directly depends on the quality of the interconnect between transmitter and receiver (and on some other factors we will see). The presence of inter-symbol interference means that receivers are not capable anymore of discerning symbols to map them into definite values and that means corrupted data. ISI is measured using a measurement technique called eye pattern measurement. So, let's take a brief moment to discuss this measurement as it is essential for the design of high-speed interconnects. For a receiver to reconstruct whether a symbol represents a specific binary value (let's say, for simplicity, a zero or a one, although a symbol may represent more than one bit as in the case of Pulse Amplitude Modulation), the receiver must be able to discern logic levels and thresholds to decide if a symbol, voltage wise, qualifies as a 1 or as a 0. Let's imagine we hook an oscilloscope at the receiving end in our interconnect, and we want to observe how deterministic the voltage levels of our signals are as we receive them. Moreover, we also want to observe if the signal is showing any noise in the time dimension (called [[#Jitter|jitter]][^15]) which could also create issues in our receiver if we cannot sample a signal always at the same time inside the pulse. Data links must have a margin in both the voltage and timing domains for proper operation. > [!info] > Let's briefly discuss signal reflection from an analog/RF viewpoint: > > In a transceiver we don’t have bits directly traversing a channel, but typically a modulated analog waveform (say QPSK, OFDM, or just an IF sine). What happens if the channel or a matching network shows reflections? >- Reflections cause part of the signal to bounce back and combine with the forward wave, creating frequency-dependent notches and ripples in the transfer function >- From the analog perspective, this looks like distortion of the amplitude and phase across frequency. That is, a “clean sinusoid” at one frequency is fine, but if you we a modulated signal with bandwidth (say 20 MHz LTE carrier), then different frequency components see different gains/phases. That means the constellation points warp or rotate differently across subcarriers. > >So what digital engineers call “ISI” in time domain, analog engineers see as group delay variation or amplitude ripple in the RF path. When characterizing channels, one single bit is not enough to statistically represent how stable a bit stream is as it travels across the interconnect; one would need to collect as many bits as possible and evaluate the dispersion in terms of amplitude and time. For this, the oscilloscope would be set for higher persistence (every time we catch one bit of the stream, it stays on the screen) so we could see the bit patterns of thousands of bits superimposed on top of each other, drawn on the screen over time. This is basically what the eye pattern measurement is. When an eye pattern test is conducted, the oscilloscope overlaps as many bits of the received signal as possible, all aligned to a common clocking signal in the case there is such a clock signal, otherwise, the test must rely on other triggering techniques such as pulse-width triggering or in modern instruments, one can also use functionalities like Protocol Trigger and Decode where the instrument can trigger on specify symbols of the protocol, typically used when testing standard interfaces like [[#PCI Express|PCIe]] or [[#Ethernet|Ethernet]] where such symbol sequences are known. Once triggered, the superimposition of waveforms results in a particular pattern on the screen (see figure below).  > [!Figure] > _Eye pattern_ When evaluating a channel's eye, a few characteristics of the plot are especially important. The wider the eye-shaped opening in the middle of the pattern, the better. A wide-open eye indicates that the receiver can clearly distinguish between symbol states, which translates to a lower probability of error in the decoded data. Conversely, a closed eye means a higher level of reflections, and loss of rising time due to [[#Losses|losses]] and [[#Jitter|jitter]], making it hard for the receiver to interpret the incoming data correctly, leading to a higher inter-symbol interference and therefore a higher bit error rate. The characteristics of an eye are described in the figure below.  > [!Figure] > _A diagram of a red diamond with white text Description automatically generated with medium confidence_ The eye measurement provides a quick and visual way to gauge the health of a high-speed interconnect. If the edges of the eye pattern are wide and/or the eye-opening is closing horizontally, this can indicate that the system is suffering from issues such as excessive jitter, if the closing is vertical, it may indicate insufficient signal amplitude, which may be caused by attenuation of the signal due to dielectric [[#Losses|losses]]. By analyzing the eye diagram, testers can determine what kind of corrective measures are needed. High-speed specifications typically describe the required eye mask. To comply with it, the waveforms of all the accumulated bits must be outside the eye mask area. The purpose of the eye mask is to account for unmeasured noise sources from the transmitter or receiver. For example, in the PCIe Gen2 transmitter specification, the eye mask is 95ps Eye Width (EW) and 225 mV Eye Height (EH), and the PCIe Gen3 TX eye mask is 41.25ps Eye Width and 46mV Eye Height for the system transmitter. > [!note] An important fact that tends to go unnoticed when it comes to signal integrity is that oscilloscopes are completely unable to measure the direction of propagation of a signal. Oscilloscopes only measure the combination of incident and reflected signals at one physical point in a circuit, projected over time. This limitation of scopes is unfortunate, as it tends to warp the engineer's intuition when it comes to signal integrity due to the instrument's inability to tell which way a signal is propagating in an interconnect under measurement. --- We said before that reflections are caused due to impedance mismatch. Let's imagine a planar, generic interconnect (such as traces in a printed circuit board or a microstrip) with the necessary two conductors—signal and return path—separated by a dielectric. Now, imagine that there is a geometry change along the way in our interconnect, creating an impedance mismatch in the path of our signal. For instance, it could be we narrow the signal trace by a few mils. We already know that [[#Transmission Lines and Characteristic Impedance of interconnects|characteristic impedance]] in microstrips depends on the width of the track, so the impedance will indeed change. How much signal would be transmitted across this impedance transition, and how much signal would be reflected? The relationship between incident signal, transmitted signal, and reflected signal in a transmission line is fundamental to understanding signal propagation and integrity because the reflected portions of the incident wave will affect our signal quality and potentially create interference. Let's first define these signals (voltages): -Incident Voltage: This is the voltage wave that originates from the source and travels down the transmission line toward the boundary where the impedance changes. It is the forward-traveling wave that would take place in an ideal transmission line with no reflections, like when the line is perfectly uniform and matched. - Transmitted Voltage: This is the voltage wave that actually passes through the impedance change boundary. In an ideal case (a perfectly matched interconnect), the transmitted voltage would equal the incident voltage, and there would be no reflected voltage. In cases of mismatch, part of the incident voltage is reflected, and the transmitted voltage is the difference between the incident and reflected voltages at the load. - Reflected Voltage: When the incident wave reaches the impedance mismatch, (meaning the impedance at one side of the boundary does not match the characteristic impedance of the other side), a portion of the wave is reflected back towards the source. ==The magnitude and phase of the reflected wave depend on the degree of the mismatch and are characterized by the reflection coefficient $\Gamma$. If the second impedance is higher than the first impedance, the reflection coefficient is positive, leading to a reflected voltage that is in phase with the incident voltage. If the second impedance is lower, the reflection coefficient is negative, resulting in a reflected voltage that is 180 degrees out of phase with the incident voltage.== The relationship between these voltages at any point on the transmission line is given by the superposition of the incident and reflected waves: $\large V_{\text{total}} = V_{\text{incident}} + V_{\text{reflected}}$ The reflection coefficient $\Gamma$ at the can be calculated as: $\large \Gamma = \frac{V_{\text{reflected}}}{V_{\text{incident}}}$ The value of $\,\Gamma$ varies between -1 and 1, where a coefficient of -1 indicates a total reflection with a sign (phase) reversal, and a coefficient of +1 indicates total reflection without a sign (phase) reversal. Calling the impedance before the discontinuity $Z_{1}$ and the impedance after the transition $Z_{2}$, in a perfectly matched interconnect without any discontinuity it would indicate that$\text{\ Z}_{1} = Z_{2}$, therefore $\ \Gamma = \ 0$, which then means $V_{\text{reflected}} = 0$ and therefore all of the incident voltage is transmitted across the boundary, meaning $V_{\text{transmitted}} = V_{\text{incident}}$. To calculate the value of the reflected voltage across an impedance change boundary, we shall use the reflection coefficient, which can be calculated using the impedances at both sides of the discontinuity as follows: $\large \Gamma = \frac{Z_{\text{2}} - Z_{\text{1}}}{Z_{\text{2}} + Z_{\text{1}}}$ Once $\,\Gamma$ is obtained, one can also get the reflected voltage $V_{\text{reflected}}$ using the incident voltage $V_{\text{incident}}$, which is the voltage wave that is initially launched onto the line: $\large V_{\text{reflected}} = \Gamma \cdot V_{\text{incident}}$ Simply replacing $\Gamma$ by $\large V_{\text{reflected}} = \frac{Z_{\text{2}} - Z_{\text{1}}}{Z_{\text{2}} + Z_{\text{1}}} \cdot V_{\text{incident}}$ This equation tells you that the reflected voltage is simply the product of the reflection coefficient and the incident voltage. #### Standing Waves When an electromagnetic wave propagates along a transmission line, the wave may reflects at discontinuities, open or shorted ends. Under certain conditions, the reflected wave interferes with the incident wave, creating a standing wave pattern. A standing wave is formed when the reflected and incident waves combine constructively or destructively, depending on the phase relationship. Standing wave pattern creates points of constructive interference. ==Because [[Physical Layer#Reflections|reflections]] are energy "stolen" from signals, a standing wave stores energy as it stays rattling around the transmission line between sources and loads.== Resonance occurs when the length of the transmission line matches an integer multiple of the wavelength ($\lambda$) or a fraction like $\lambda/2$ or $\lambda/4$. This happens because the geometry supports standing waves with nodes and antinodes that align perfectly with the line's boundaries. ##### At Multiples of $\lambda/2$: 1. **Open Ends** (Voltage Maximum, Current Minimum): - An open circuit acts as a voltage antinode (maximum voltage) and a current node (zero current). - If the line length is $L = \frac{\lambda}{2}, \lambda, \frac{3\lambda}{2}, \dots$, the reflected wave perfectly aligns with the incident wave, reinforcing the oscillations. 2. **Shorted Ends** (Current Maximum, Voltage Minimum): - A short circuit acts as a current antinode (maximum current) and a voltage node (zero voltage). - Similarly, resonance occurs when $L$ is a multiple of $\lambda/2$. ##### At $\lambda/4$ and Odd Multiples: 1. At $\lambda/4$, one end may act as a voltage maximum (open circuit) and the other as a current maximum (short circuit). 2. The quarter-wavelength supports standing waves because the reflected wave phase-shift matches the incident wave. ![[Pasted image 20250103111121.png]] > [!Figure] > _Standing wave patterns example_ (source: https://commons.wikimedia.org/wiki/File:StandingWave.png) A standing wave requires an integer number of half-wavelengths to fit exactly within the length of the transmission line (see figure above). At these lengths, the wave reflections reinforce the original wave rather than cancel it, satisfying the conditions for resonance. There is a way of quantifying the standing waves by using the VSWR (Voltage Standing Wave Ratio), and it does so by measuring the ratio of the maximum to the minimum voltage amplitude along the transmission line. $\large \text{VSWR} = \frac{V_{\text{max}}}{V_{\text{min}}}$​ - $V_{\text{max}}$​: The maximum voltage amplitude of the standing wave. - $V_{\text{min}}$​: The minimum voltage amplitude of the standing wave. The VSWR is related to the magnitude of the reflection coefficient we discussed before ($\Gamma$): $\large \text{VSWR} = \frac{1 + |\Gamma|}{1 - |\Gamma|}$ - $|\Gamma$| = 0, $\text{VSWR} = 1$, perfect impedance match - $|\Gamma| = 1$, $\text{VSWR} = \infty$, total reflection, all energy is reflected A typical way of reading VSWR is as ratios (e.g., 1.1:1), which would flag a good match, as most of the power is delivered to the load. In contrast, a high VSWR (e.g., 5:1), would indicate poor impedance matching, meaning that a significant power is reflected. Note that standing waves and VSWR are more prevalent when launching AC waveforms through the interconnect. In high-speed digital design, standing waves can manifest if excited by certain harmonics of the digital pulses. Standing waves find more application in RF and [[Antennas|antennas]]. #### Impedance Matching between Drivers and Receivers We have a bigger problem than we thought: even while having perfectly uniform interconnects, we can still have reflections. How so? For example, if we connected a driver and a receiver through a perfectly matched transmission line, we could still have impedance transitions between the low output impedance of drivers (typically a few ohms) and the interconnect, but also between the typically high input impedance of receivers and the interconnect.  > [!Figure] > *A driver and a receiver connected through a 50-ohm transmission line.* If our driver launched a 1 Volt signal through the interconnect, that 1 Volt voltage wave would find a high impedance when reaching the receiver—this would give a $\Gamma$ = 1—which means the signal would fully reflect, and the reflected signal would then propagate and eventually find the low output impedance of the driver—a reflection coefficient $\Gamma$ = -1—which in turn would reflect the signal back but changed in sign. The result? We would observe an unpleasant ringing in the line if we hooked a scope (see figure below). Is this harmful? Well, it depends on the frequencies involved in the data interface. For low-speed data rates, the ringing would mostly be harmless. For high-speed data, this would mean Inter Symbol Interference. As we can see, high-speed data interfaces put stronger pressure on the quality of our designs: the higher the speed, the higher the quality required of our materials, our manufacturing processes, our layouts, routing topologies, and the components we use, like connectors.  > [!Figure] > *Ringing in signals due to reflections at driver output and receiver input. Source: [AN022](https://www.diodes.com/assets/App-Note-Files/AN022-P.pdf?v=1), Diodes Incorporated)* How do we fix this? With termination resistors. Termination resistors are typically matched to the characteristic impedance of the interconnect and connected at the receiving end, and not the impedance of the receiver. Using termination resistors creates a condition where the incident energy is fully absorbed by the resistor, minimizing the reflections. For the best effect, the termination resistor must be placed as close to the receiver as possible. This helps to ensure that the signal sees the matching impedance at the point where it would otherwise reflect. For instance, if the transmission line has a characteristic impedance of 50 ohms, a 50-ohm resistor would be used for termination. In a practical scenario where we have a low-output-impedance driver and a high-input-impedance receiver, here's what we can use: -Far-end Parallel Termination: One must add a resistor equal to the characteristic impedance of the transmission line in parallel with the input impedance of the receiver at the receiver end. This way, the signal sees the characteristic impedance of the interconnect once it reaches the receiver (remember the receiver input impedance is high) and the reflected energy is absorbed by the resistor, which will generate heat. In far-end termination, the output impedance of the driver and the termination resistor will form a voltage divider, which means that the receiver will not receive the full swing of the source, impacting the voltage noise margin and affecting the eye pattern. One way of working this issue around is to connect the parallel resistor to half of the supply chain voltage to center the eye. Variations of the far-end termination include RC termination (not great for signals that do not have a 50% duty cycle, therefore it's popular for clocks that do have 50% duty cycle), and Thevenin termination. The far-end termination still suffers from a drawback: the length of the trace between the termination resistor and the actual receiver inside the chip (including the package lead and the wire bond between the lead and the die) will create a stub which will impact signal integrity. At faster rise times, the more reflections this stub will create, therefore the higher the resulting inter-symbol interference. The only viable solution for this is built-in termination resistors inside the actual chip (called on-die termination). If on-die termination is not a possibility, there is still one strategy in the toolbox: fly-by termination, which means placing the termination resistor **after** the receiver. It's called fly-by because the signal wave "flies by" the receiver to reach the termination resistor after passing it. Both approaches are shown below. > [!Figure] > *Far-end parallel termination*  > [!Figure] > _Fly-by termination_ -Source series termination: the idea of this termination technique is to let the reflection happen and to add a series resistance on top of the driver's low output resistance in a way that, combined, matches the characteristic impedance of the interconnect. The source series combined with the characteristic impedance of the interconnect form a voltage divider, therefore, during the first trip of the voltage incident wave, the receiver will see half the voltage. But because the input impedance of the receiver is high, the reflection coefficient will be 1 therefore the signal will be fully reflected, adding to the incident wave and stabilizing into the full voltage after the first "shelf". When using source series termination, the signal only looks good at the end of the interconnect, right at the receiver. > [!Figure] > _Source series termination_ By selecting and placing termination resistors, the system impedance can be effectively matched, and reflections are minimized, which improves signal integrity. Note that different termination strategies have different power consumption profiles, which may drive the decision-making during the design stage if the design must prioritize low power consumption. > [!info] > The lowest power-hungry termination technique is source series termination. It's also worth noting that while terminating the line properly is important for high-speed signals, for slow signals, it may not be necessary due to the negligible impact of reflections on signal integrity. There are plenty of practical scenarios that can cause impedance discontinuities in interconnects linking transmitter and receivers, for example: - Geometrical changes along the PCB tracks (including stubs, vias, neck downs, corners, etc.) - PCB dielectric quality - Connectors - Routing topologies - Component placement errors - Solder quality To ensure data integrity from end to end in a channel, certain specifications of the drivers and the receivers used in said channel must be known. For the drivers, the most important features are output impedance and rise time. When it comes to receivers, although the impedance is quite high and one could consider it an "open circuit", there will be a small amount of input gate capacitance that needs to be considered. Typically, the input capacitance is given by the input pad of the receiver but also by ESD diodes, which are good for robustizing the devices during handling but will increase the input capacitance. Input capacitance will present itself as a low impedance for high frequencies, and cause reflections. Time-domain reflectometry (TDR) is typically used for measuring input capacitance[^16], which typically ranges between 1 to 8pF. #### Routing Topologies ==As we discussed at the beginning of this section, the sole source of reflections is changes in instantaneous impedance. Therefore, the solution for this transpires as rather simple: one shall not introduce changes or discontinuities in the instantaneous impedance.== Granted, easy to say. Not so easy to achieve. As we push data rates higher, significant problems will appear as we route signals in our designs. The way signals will branch from the source will greatly affect the signal integrity. Signal branching, we will see, is a luxury we will not be able to afford at high data rates. At a certain point, linear routing topologies (i.e., point-to-point) will be the only practical way of engineering signal interconnects. Let's explore for a moment the different topologies we have at hand: - Point-to-point - Branched - Tree - Linear Routing topologies play a critical role in signal integrity, particularly concerning reflections. Each routing topology has its characteristics that can either mitigate or exacerbate signal integrity issues such as reflections. ##### Point-to-Point Routing This is the simplest form of routing where a single driver sends signals to a single receiver along a dedicated path. **Pros**: Point-to-point provides the cleanest signal integrity scenario because there is only one path for the signal to travel, minimizing potential reflection points and discontinuities. It's easiest to match the impedance throughout the entire length of the trace, ensuring minimal reflections. **Cons**: It's not scalable for connections to multiple receivers, as it would require separate traces for each connection, leading to increased PCB complexity and real estate usage.  > [!Figure] > _Point-to-point routing_ ##### Branched Routing In branched routing, a single driver connects to multiple receivers through a series of branches from the main trace. **Pros**: It allows one driver to connect to several receivers, which can save space compared to multiple point-to-point connections. **Cons**: Each branch point can create a reflection due to the impedance discontinuity. The signal can reflect back toward the source at each branch, leading to signal integrity issues, especially at higher frequencies.  > [!Figure] > _Branched & tree routing topology._ ##### Tree/Clustered Routing Similar to branched routing but with a more hierarchical structure, where branches themselves can have further branches. **Pros**: This can be efficient in terms of space for complex connections and can be organized in a hierarchical manner that reflects the system's architecture. **Cons**: Like branched routing, it suffers from multiple points of potential impedance discontinuity and reflections. Signal timing can also become complex, as different branches may have different lengths, causing signal [[#Line-to-Line Skew|skew]]. ##### Linear (Daisy-Chain) Routing Signals are routed from one device to the next in a chain, with each device connected in series along the signal path. Pros: Linear routing simplifies the design and can be easier to lay out than other multi-drop systems. Cons: Reflections can be a significant problem due to the signal passing through multiple connectors or devices, each adding a potential mismatch in impedance. Also, the failure of a single device or connection in the chain can disrupt the entire communication path.  > [!Figure] > _Linear routing topology_ Further ahead, we will explore the particularities of board layout design and how our routing decisions are also shaped by manufacturability requirements. > [!info] Thinking in dBs When discussing signal integrity, we must get very familiar with signal ratios, as we are most of the time interested in the relationship between transmitted, received and reflected quantities and not so much about their absolute values. When working with ratios, the decibel (dB) appears a great unit to work with. A dB is always, without exception, ten times the logarithm of the ratio of two powers: $\large dB\ = \ 10\ log\ \frac{P_{1}}{P_{0}}$ When we use reference values as denominators of our ratios, we can then use standard measurements which helps to compare. For instance, using a power of 1W as a ratio reference, we can measure any other power in dB of power. When we use 1mW as the reference power level, we often designate the dB as dBm to identify that the reference power is 1mW. Then, we can compare the dBms of power output of a transmitter from supplier A with the output power of supplier B. But we can also use dBs to compare quantities that are not powers. To do so, we have to somehow convert them into powers so we can use the dB scale. Voltage isn't power, but amplitude. To use the dB scale to describe a voltage, we have to convert the voltages into powers and take the ratio of the powers that are related to the voltages. For example, the power dissipated in a resistor by a voltage, V, is V²/R. We can describe the ratio of the power generated by two voltages if they were across the same resistor, as: $\large 10\ log\ \frac{P_{1}}{P_{0}}\ = \ 10\ log\ \frac{{V_{1}}^{2}}{{V_{0}}^{2}}$ The resistances, of course, cancel out. We can pull the square terms out of the log and get: $\large 10\ log\ \frac{{V_{1}}^{2}}{{V_{0}}^{2}} = \ 10\ 2\ log\ \frac{V_{1}}{V_{0}}\ = \ 20\ log\ \frac{V_{1}}{V_{0}}$ That's where the factor of 20 comes from. Whenever we describe the ratio of two things that are not powers, but amplitudes, we use a factor of 20 to get back to the original ratio. The value in dB is really about the ratio of the powers of the two quantities we are comparing. The factor of 20 lets us convert to the log of the ratio of the voltages. Then, we can calculate the ratio of two signals from a known value in dB as: $\large \frac{V_{\text{output}}}{V_{\text{input}}} = 10^{\frac{A_{\text{dB}}}{20}}$ We can then put some ratios and see their equivalence in dB: > > |Voltage ratio | dB| > |-------------|----| >|1 | 0| >|0.9 | -1| >|0.8 | -2| >|0.7 | -3| >|0.5 | -6| >|0.3 | -10| >|0.1 | -20| >|0.05 | -26| >|0.03| -30| >|0.01| -40| ### Scattering Parameters As we said, interconnects are far from perfect. They interact with our signals and affect their quality, potentially introducing errors in our bit streams of data. But how to characterize interconnects in a way we can analyze, in a reasonably quantitative manner, how an interconnect will affect our signals even before we have the chance to measure anything? The way is by utilizing scattering parameters, or S-parameters. Succinctly, S-parameters are a method to describe the behavior of interconnects following a particular format. In a nutshell, everything we ever wanted to know about the electrical behavior of interconnects is contained in their S-parameters. They are called "scattering" parameters because they fundamentally work by describing how the signal scatters off an interconnect in a set of directions: - How much of the signal is injected into the interconnect (incident wave) - How much of the signal scatters back (reflected wave, denominated $S_{11}$ and called "return loss" or "reflection coefficient") - How much of the signal goes through (transmitted wave, denominated $S_{21}$ and called "insertion loss", or "transmission coefficient") Note that when insertion loss increases, there is less received signal at the output port. When return loss increases, this means there is little signal reflected to the input put, and the device under test (DUT) is a good match to the fixture. When the interconnect is symmetrical from one end to the other, the return losses, $S_{11}$ and $S_{22}$, are equal. In an asymmetric two-port interconnect, $S_{11}$and $S_{22}$will be different. S-parameters describe the way electrical signals behave when they interact with the interconnect. From this behavioral model, it is possible to predict the way any arbitrary signal might interact with the interconnect, and from this behavior, we can predict output waveforms, such as an eye diagram. S-parameters are strictly about signals, and in particular about ratios of signals. An important pre-requisite to working with S-parameters is that our interconnects must be linear, passive, and time-invariant, which includes 99% of all the interconnects out there[^17]. The versatility of S-parameters is that they can work in the time domain and frequency domain, and we can use these parameters to convert between both domains using some algebra. The formal definition of S-parameters requires us to define interconnects as boxes with ends that we will call ports: $\large S_{\text{jk}} = \frac{\text{sine\ wave\ out\ of\ port\ j}}{\text{sine\ wave\ into\ port\ k}}\ $ Note that the first element in an S-parameter is the output port, whereas the second one is the input port. One may also want to know the ratio between the incident and reflected signal on the same ports. The phase of the S-parameter is the phase difference between the output wave minus the input wave: the order of the waveforms in the definition of the phase of the S-parameter will be important when determining the phase of the reflected or transmitted S-parameter and will contribute to a negative advancing phase. Although phase information in s-parameters tends to be somewhat neglected, it may provide useful information about an interconnect; for instance, the phase of $S_{21}$ parameter is directly related to the time delay in an interconnect. The phase of $S_{21}$ shows the phase shift that a signal undergoes as it travels from port 1 to port 2. This phase shift can be caused by various factors, including the properties of the material, the length of the transmission path, and other circuit elements. A phase shift can be translated into a time delay using the frequency of the signal. The relationship is given by the formula: $\large TD\ = \ \frac{\text{Phase\ shift}}{360}\text{x\ }\frac{1}{\text{frequency}}$ This means that if you know the phase shift in degrees and the frequency of the signal, you can calculate the time delay. The worse the interconnect and the larger the impedance mismatch to the port impedances, the closer the return loss will be to 0 dB, corresponding to 100% reflection. The insertion loss is a measure of the signal that transmits through the device and gets out of port 2. The larger the impedance mismatch, the less transmitted signal. However, when there is close to a good match, the insertion loss is very nearly 0 dB and is insensitive to impedance variations. ==Considering the inescapable law of conservation of energy, if the interconnect is low loss, there is no coupling to adjacent traces, and there are no radiated energy, then the energy into the interconnect must be the sum of the reflected energy and the transmitted energy.== It is always important to keep in mind that the S-parameters are ratios of voltages. This means that to describe an S-parameter in dB, we use the factor of 20 to relate the log of the ratio of the output voltage from some port compared to the input voltage. Thus, the value of the S-parameter in dB is: $\large S_{\text{jk}}\lbrack dB\rbrack = 20\ log\frac{\text{Voltage\ out\ of\ port\ j}}{\text{Voltage\ into\ port\ k}}$ An $S_{11}$ with a value of -20dB means a reflected voltage signal that is 10-20/20 = 10% of the incident voltage signal. Because power scales as $S_{11}$², the power reflected is 1% of the incident power, which is 10-20/10 = 1%. This is a reasonably good value for most digital interconnect structures. A value of an output power of -3 dB means that the ratio of output to input power is 10-3/10 = 0.5. But this is a 50% drop in the power level. What happens to the voltage level? A value of -3dB is always a 50% drop in power, but the ratio of output voltage to input voltage is 10- 3/20 = 70%. When $S_{21}$ is -3dB, the voltage level of the signal coming out of the interconnect is 70% of the voltage that went in. When we refer to the SNR (signal-to-noise ratio), we usually measure it in dB as well. Without exception, the SNR in dB always refers to the ratio of the power between the signal and the noise. An SNR of 20 dB means the signal power is 100x the noise power. The same SNR of 20 dB, a signal power which is 100x the noise power, is at the same time, a signal voltage of 10x the noise voltage. Isolation of noise to signal of -60 dB is a noise power that is 10-60/10 = 1,000,000 times smaller than the signal power. But the voltage noise is only 10-60/20 = 1,000 times smaller than the signal voltage. ##### Touchstone File Format The usefulness of S-parameters lies in their capability to commonalize a way of characterizing and comparing interconnects. S-parameters are typically obtained by measuring interconnects, and the data stemming from the measurements tends to be packaged in files that can be shared between designers. Thus, it is convenient for the format of those files to be standardized. One such format is Touchstone files. The S-parameter Touchstone file format, commonly referred to as the Touchstone format, is an industry-standard method for storing and sharing data on network parameters, particularly scattering parameters (S-parameters). Developed initially in the 1980s by Hewlett-Packard (now Keysight Technologies), the format has become a universal standard for representing network analysis data. This format is widely used by engineers and scientists in the fields of RF and microwave engineering. The Touchstone file, typically with a .snp extension (where 'n' denotes the number of ports), encapsulates this data in a format that is both human-readable and machine-parseable. The most common format is the two-port S-parameter file, denoted as '.s2p'. The file consists of a series of frequency points, at each of which the S-parameters are defined. These parameters are complex numbers, representing both magnitude and phase and are usually presented in either a rectangular (real and imaginary) or polar (magnitude and phase) format. The Touchstone file begins with a header section, which includes metadata such as the frequency units (MHz, GHz, etc.), the network parameter type (S, Y, Z, etc.), and the data format. Following the header is the data section, where each line represents a different frequency point and contains the corresponding S-parameter data. Here's an example of what a basic two-port S-parameter Touchstone file (.s2p file) might look like: ``` # GHz S DB R 50 ! Sample 2-port S-Parameter Data ! Freq S11 S21 S12 S22 1.000 -3.52 130.0 -0.10 3.0 -3.60 135.0 -0.20 6.0 2.000 -6.23 145.0 -0.15 4.5 -6.45 150.0 -0.25 7.5 3.000 -9.10 160.0 -0.20 6.0 -9.30 165.0 -0.30 9.0 ``` The first line \# GHz S DB R 50 is the header line. The symbol '\#' indicates that this line is a comment or a header. - ```GHz``` specifies the frequency unit (Gigahertz in this case). - ```S``` indicates that the parameters are S-parameters. - ```DB``` flags that the data is in decibels and degrees (magnitude in dB and phase in degrees). - ```R 50``` means the data is referenced to a 50-ohm characteristic impedance system. The second and third lines, starting with '!', are comment lines providing additional information. They are not processed by most software but are useful for human readers. The subsequent lines contain the following data: - The first column is the frequency. Here, it's in GHz, as specified in the header. - The next pairs of columns represent the S-parameters: $S_{11}$, $S_{21}$, $S_{12}$, $S_{22}$. Each S-parameter is represented by two numbers: the first is the magnitude in dB and the second is the phase in degrees. In this example, at 1 GHz, $S_{11}$ is -3.52 dB at 130 degrees, $S_{21}$ is -0.10 dB at 3 degrees, $S_{12}$ is -3.60 dB at 135 degrees, and $S_{22}$ is -0.20 dB at 6 degrees. The pattern repeats for 2 GHz and 3 GHz. ##### Differential S-Parameters (Mixed Mode) Two independent transmission lines in proximity and with coupling can be described in two equivalent ways. On the one hand, they are two independent transmission lines, each with independent properties. For example, if we use the labeling scheme suggested before, where port 1 goes through to port 2 and port 3 goes through to port 4, each transmission line would have reflected elements, $S_{11}$ and $S_{33}$, and each would have a transmitted element, $S_{21}$ and $S_{43}$. In addition, there would be cross-talk between the two lines. The near and far-end noise signatures would vary depending on the spacing, coupling lengths, and topology. All the electrical properties of these two transmission lines are completely described by these S-parameter elements across the frequency range. However, these same two lines can also be described as one differential pair. No assumptions have to be made about the lines; this description as a differential pair is a complete description. But the words we use and the behavior we describe are very different for a single differential pair description than for two independent single-ended transmission lines with coupling.  > [!Figure] > _Two single-ended transmission lines with coupling are not the same as a differential pair when thinking of scattering parameters_ From the figure above, note that, as a convention, the ports are assigned as an odd port on the left end of a transmission line and the next higher number on the other end of the line. This way, as the number of coupled lines increases, additional index numbers can be added by following this rule. We said when introducing S-parameters that these are about ratios of signals. In differential S-parameters, the statement of course still holds: differential S-parameters are about differential signal ratios (how much differential signal is transmitted versus reflected, for example). But differential S-parameters are also about common signal ratios and combination ratios between differential and common signals. A differential signal will be composed of two voltages fed into the transmission line with a 180-degree phase difference. When feeding this differential signal into the 2-line interconnect, the signal will see a series combination of the single-ended impedances of each line. For two 50-ohm lines, a differential signal will see 100 ohms. Conversely, a common signal will be any two signals in-phase added into the two transmission lines. The impedance a common signal will see is 25 ohms. Differential S-parameters are also referred to as "mixed-mode" S-parameters or "balanced" S-parameters. They all refer to differential parameters. The nomenclature of differential S-parameters is straightforward: - $S_{DD}$: Differential signal goes in, differential signal out - $S_{CC}$: Common signal goes in, common signal out - $S_{CD}$: Differential signal goes in, common signal out - $S_{DC}$: Common signal goes in, differential signal out When it comes to the combinatorial ratios between ports 1 and 2 of a differential pair, this describes a matrix between stimulus and response, which is depicted in the figure below.  > [!Figure] > _Mixed mode S-parameter matrix and the meaning of each quadrant (source: https://www.signalintegrityjournal.com/articles/432-s-parameters-signal-integrity-analysis-in-the-blink-of-an-eye)_ ##### Conversion between Single-Ended and Differential S-Parameters Converting from the 4-port single-ended S-parameters to the 2-port differential S-parameters comes in handy when analyzing differential signal pairs. The conversion involves using the single-ended S-parameters of a 4-port network to compute the differential-mode S-parameters of a 2-port network. Given the 4-port single-ended S-parameters $S_{\text{ij}}$ (where $\ i,\ j\ = \ 1,\ 2,\ 3,\ 4$, the 2-port differential S-parameters $S_{\text{DD}}$ can be computed as follows: - Differential Input Reflection Coefficient (also known as return loss) $\text{SDD}_{11}$: $\large \text{SDD}_{11} = \frac{1}{2}\left( S_{11} - S_{13} - S_{31} + S_{33} \right)$ - Differential Output Reflection Coefficient (return loss) $\text{SDD}_{22}$: $\large \text{SDD}_{22} = \frac{1}{2}\left( S_{22} - S_{24} - S_{42} + S_{44} \right)$ - Differential Transmission Coefficient (or insertion loss) $\text{SDD}_{21}$: $\large \text{SDD}_{21} = \frac{1}{2}\left( S_{21} - S_{23} - S_{41} + S_{43} \right)$ - Differential Reverse Transmission Coefficient (insertion loss) $\text{SDD}_{12}$: $\large \text{SDD}_{12} = \frac{1}{2}\left( S_{12} - S_{14} - S_{32} + S_{34} \right)$ It's important to remember that each S-parameter contains an amplitude and a phase. The conversion from 4-port single-ended S-parameters to 2-port differential S-parameters can be more elegantly expressed using matrix algebra. Let's denote the single-ended S-parameter matrix as $S$ and the differential S-parameter matrix as $\text{SDD}$. The matrices are defined as follows: The single-ended 4-port S-parameter matrix $S$ is: $\large \mathbf{S}\ = \ \begin{matrix} S_{11} & S_{12} & S_{13} & S_{14} \\ S_{21} & S_{22} & S_{23} & S_{24} \\ S_{31} & S_{32} & S_{33} & S_{34} \\ S_{41} & S_{42} & S_{43} & S_{44} \\ \end{matrix}$ The 2-port differential S-parameter matrix $\text{SDD}$ is: $\large \mathbf{\text{SDD\ }} = \ \begin{matrix} \text{SDD}_{11} & \text{SDD}_{12} \\ \text{SDD}_{21} & \text{SDD}_{22} \\ \end{matrix}$ The conversion formula can be represented as a matrix operation: $\large \mathbf{\text{SDD}} = \frac{1}{2}M \times S \times M^{T}$ where $M$ is a mode conversion matrix defined as: $\large M\ = \ \begin{matrix} 1 & 0 & - 1 & 0 \\ 0 & 1 & 0 & - 1 \\ \end{matrix}$ and $M^{T}$ is the transpose of $M$. We can now finalize the analysis on S-parameters in single-ended and differential pairs. In loosely coupled transmission lines, $S_{23}$ and $S_{41}$ will be zero. $S_{13}$ and $S_{31}$ will also be zero. If the lines are symmetrical, then $S_{21}$ and $S_{43}$ (the lines' insertion losses) should be expected to be the same. In this case, when both lines are far from each other (no coupling) and the lines have roughly the same geometry, the single-ended response will be identical to the differential response, therefore $SDD_{21}=S_{21}$ and $SDD_{11}=S_{11}$. If there is coupling and also asymmetry between the lines, $SDD_{21}$ will be different than $S_{21}$. ==But what is all the fuss about the coupling or not in a differential pair? When designing differential pairs, discontinuities in the return path may cause an increase in the differential impedance of the pair. To keep the differential impedance close to 100 ohms, one can play with the coupling between the lines; in this case, to make the differential impedance 100 ohms, both conductors of the differential pair must be brought close together. That's the importance of a tightly coupled differential interconnect.== > [!info] > When measuring the parameters of cables and interconnects, it is common to employ de-embedding. De-embedding is a process used to isolate the behavior of a particular component or part of a system from the overall measurement. In signal integrity, the measurements are often influenced by various elements such as cables, connectors, probes, and fixtures used in the test setup. These additional elements can introduce distortions or anomalies in the signal, making it difficult to accurately assess the performance of the device under test (DUT). De-embedding involves mathematically removing the effects of these extraneous elements from the measurement data. Without de-embedding, it would be challenging to determine whether a signal integrity issue is due to the DUT or due to the test setup. The process starts with characterizing the test fixtures and interconnects. This involves measuring their properties, like impedance, reflection, and transmission losses, using known standards. Once these characteristics are understood, they can be mathematically subtracted from the overall measurement. This subtraction is done using specific algorithms and models that accurately represent the behavior of the test setup components. De-embedding ensures that the final measurement data reflects only the performance of the DUT, free from the influences of the test setup. ##### Concatenation of parameters > [!warning] > This section is under #development #### What are S-Parameters Used For? We said in previous sections that S-parameters help us gain information about the properties of interconnects. Picture now that someone has just given us an S-parameter model in the form of a Touchstone file. What do we do with it? The typical use case for S-parameters is to use them as a black box model. This way, we can use the model that we have been given as a descriptive representation of some unknown interconnect structure, and we can plug the model into the rest of our system simulation to evaluate how that component is going to behave in our design. Ideally, we probably don't care too much about what's going on inside this black box. We don't have to open up the *lid* to use it in our design as long as we trust the source. Of course, this requires having high confidence in the quality of the models we work with. The reality is that, if we are going to just grab the model from a vendor and throw it into our circuit simulation and get a result, we will have no idea how good or bad that result is going to be. If we want to have full confidence in the result of our system simulation, then we must be able to open up the lid, take a look at that black box model, and evaluate whether it is a good model or not. S-parameters are useful as a medium of exchange of information and comparison. Having two interconnects, we can quantitatively compare the two, for instance using the insertion loss as a figure of merit. For instance, if we needed to ensure that an interconnect is compliant with some standard spec, we could just compare the S-parameters of the interconnect with what the specification requires. In this case, we would not even need to know what the meaning of insertion loss is, as long as the numbers match. Again, the process appears quite fragile because, if the figures from the model and the spec are not the same, we will not know what to do with the information. Another scenario of comparison would be between an S-parameter model and lab measurements. As long as the plots from the model and the measurement match, we are still free from diving into the numbers. But we cannot escape too long from doing that, because sooner or later numbers will not match. Opening up the lid transpires as quite important. Another factor to consider is how to extract useful metrics out of S-parameter models. For any interconnect, the most important metric it will ever have is its characteristic impedance. If we know the characteristics of the interconnect, we know a lot about it; we can tell almost exactly and instantly how the interconnect is going to behave in our system application. Now, if all we get are the S-parameters for the interconnect cable, what do we actually obtain? For a start, we will have four different parameters ($S_{11}$, $S_{12}$, $S_{21}$, $S_{22}$), each one being complex. Then, the Touchstone file will have eight different columns of data, two columns per parameter (real and imaginary parts). If the model is measured from, say, 10MHz to 10GHz at every 10 MHz, that's 1,000 frequency data points per parameter, therefore we will have 8,000 different numbers. Which one of those 8,000 numbers is the characteristic impedance? We only want one number; characteristic impedance. How do we get it? ##### Extracting $Z_0$ In fact, buried in those 8,000 numbers indeed lies the characteristic impedance, but we have to do some data mining to get that one number out. We must open up the black box to extract this one number. One way could be to take the S-parameter model for our interconnect and re-simulate it with different port impedances until nothing reflects back. When in fact nothing reflects, it means the port impedance compared to the characteristic impedance match. That's a quick, easy way of doing it; not a lot of calculation involved. Another way of doing it would be to calculate inductance and capacitance and use the known formula of [[Physical Layer#Transmission Lines and Characteristic Impedance of interconnects|characteristic impedance]]. How do we get the capacitance? We can use $S_{11}$ while having the far end of the interconnect open. To get the inductance, we will do the same but short the far end instead. We then use the known formula and compute $Z_0$ from the square root of the L over C. Another way is to perform a TDR measurement, where we measure $S_{11}$ (reflection coefficient, or return loss) in the time domain by sending a test signal in—for instance, a step signal—and looking at what reflects and from how much reflects we devise the characteristic impedance following the formulas we explored before. As we can see, we can in fact process the S-parameters to go from 8,000 loose numbers to that one metric that we need. But it inevitably requires us to open up the black box and crunch some numbers. ##### Extracting Time Delay Besides de characteristic impedance, we might want to know the time delay of our interconnect. Again, we can inject a step response, and look at how much signal goes through, that is, observing the $S_{21}$ parameter in the time domain. We take the phase of $S_{21}$, divided by frequency, and we get the time delay as a function of frequency. ##### Extracting losses Another metric that we might want to obtain is the interconnect's attenuation; i.e., the loss in the cable. To observe [[Physical Layer#Losses|losses]], we must look at the $S_{21}$ as a function of frequency, which will most likely drop off monotonic with frequency. If we compute that attenuation per unit of length per gigahertz, we'd get numbers that can help us decide how physically long our interconnects can go before the intersymbol interference gets out of bounds. Or, equivalently, if the channels must go longer distances than what the losses indicate, we can decide to use [[Physical Layer#Equalization|different techniques]] to compensate for the effect of losses. Obtaining losses in an interconnect is a figure of merit that is scalable and gives us a quick idea of the properties of the interconnect. But again, it requires us to open up the black box. As we can see, processing a bit of S-parameters is a powerful way of extracting a few simple figures of merit that will describe in great detail interconnects. ##### Extracting Circuit Topology There's one more thing that we can do with the S-parameters, perhaps a tad more sophisticated. We can extract circuit topology to get a scalable model of the interconnect. What if we needed to know the performance of the interconnect if we doubled its length? We just can't manipulate the S-parameters and pretend we could tweak them to get the parameters for something twice as long. We must go back to the source and re-generate them all over again for this other longer interconnect. S-parameters are not scalable. S-parameters are a point solution for a specific geometry of an interconnect. If we want to know what would happen if we paid a little extra and used a different dielectric material in a different dielectric constant, a different dissipation factor, there's no easy knob to tweak in the S-parameters to scale those elements. We must go back to the source that generated them, either build it and measure it, or re-simulate it. If we wanted a scalable model to explore design space a little bit, we would have to take the S-parameter model for that interconnect and approximate it by combinations of lumped circuit elements like inductors and capacitors that are scalable. Taking the S parameters and turning them into a circuit is an empiric, iterative craft. It requires some trial and error until we get enough agreement between the simulated response to that circuit topology and the S parameters we are trying to match it to. There is this famous phrase that says that all models are wrong, but some are useful. S-parameters are a model, a representation. So, they bring all the pros and cons of working with such abstract representations of a system. How well can we trust the model? Is it an accurate model? That is hard to tell. The key for designers is to always be sure of what they expect to see, and work with a critical eye while being always ready to open the lid. ### Losses An empirical rule of thumb in most bibliographies on signal integrity says that, for data rates below 1 Gbps, one can relax and not worry too much about losses. Where is that magical number coming from? In FR4 material, a 50-ohm, 5-mil wide line of roughly 30 centimeters in length would present a rise time of around a nanosecond (this is geometry-dependent so we may need a solver to get that number accurately). If the unit interval of the signal is lower than that, we probably do not care too much. Now, if our unit interval is shorter than a nanosecond, losses may in fact affect the rise time of our signal and collapse our eye pattern. What are these losses about, anyway? When we connect a driver and a receiver through an interconnect, we want the entirety of the signal we transmit to arrive at the receiver. That is, we want not only the fundamental frequency but also all relevant harmonics so our signal would keep its ideal shape. In most cases, less signal arrives compared to what we launched. The reason? Conductor losses and dielectric losses, both being frequency-dependent. In the conductor, the main mechanism for losses is series resistance resulting from the skin effect, which increases series resistance with the square root of frequency. The other loss mechanism is related to the dielectric between signal and return, and the interaction of the dipoles that compose the polymers used in the dielectric aligning with the changing electric fields of our signal wavefronts. The motion of these dipoles creates mechanical friction which translates into heat. As frequency increases, the dipoles vibrate faster with said electric fields, more energy is absorbed by the material, and the higher the amount of heat dissipated, hence higher the losses. With all this, if we inject a signal—say, a pure sinusoidal tone—in one side of the interconnect, these losses will cause a smaller amplitude will be received at the other end. The ratio between the received amplitude versus de transmitted amplitude is called, as we discussed, transmission coefficient or insertion loss. The graph below shows the attenuation in a 50-ohm channel due to conductor and dielectric losses (combined, in blue). While [[Physical Layer#Reflections|reflections]] are energy "stolen" from our signals rattling around the channel between sources and loads; losses are just dissipated energy that is lost due to the mechanisms we described above.  > [!Figure] > *Attenuation in a 50-ohm stripline per contributor (conductor & dielectric). Credit: Polar Instruments.*  > [!Figure] > *Simulated transmitted signals at the output of a 30-inch-long transmission line for a roughly 50-psec rise-time input signal with no loss (blue), with conductor loss for an 8-mil-wide trace (red), and with combined conductor and dielectric loss for a dissipation factor of 0.02 (green), showing the increasing rise-time degradation (Source: #ref/BogatinBook)* The fact our interconnects show a frequency-dependent attenuation means that, if we injected a square signal in our interconnect, the signal coming out would not be as square. We know these square signals are composed of many harmonics, that is, a series of sine waves at different frequencies and amplitudes combined, where the fundamental frequency is its basic frequency, and the (odd) harmonics are at integer multiples of this fundamental frequency, with the amplitude of each harmonic being inversely proportional to its order. Therefore, because the higher frequency components of a square signal will be attenuated due to the "lowpass" behavior of the transmission line, this means the signal will be less square. In other words, the signal will increase its rise time (see figure right above). As we said, if the signal's unit interval (UI) is short compared to the rise time, the signal edge will not rise fast enough to reach the relevant logic levels, increasing inter-symbol interference. It is not the loss itself that causes rise-time degradation and ISI, but the frequency dependence of the loss. Here we illustrate the effect with a Python example: ```python import numpy as np import matplotlib.pyplot as plt from scipy import signal # Generate a square wave signal fs = 1000 # Sampling frequency in Hz t = np.arange(0, 1, 1/fs) # Time vector f_square = 5 # Frequency of the square wave x_square = signal.square(2 * np.pi * f_square * t) # Simulate a lossy channel with a low-pass filter fc_lowpass = 30 # Cutoff frequency of the low-pass filter (Hz) b, a = signal.butter(4, fc_lowpass / (0.5 * fs), 'low') x_filtered = signal.filtfilt(b, a, x_square) # Plotting plt.figure(figsize=(12, 6)) # Original square wave signal plt.subplot(2, 1, 1) plt.plot(t, x_square) plt.title('Original Square Wave Signal') plt.xlabel('Time [s]') plt.ylabel('Amplitude') plt.grid(True) # Square wave signal after passing through a lossy channel plt.subplot(2, 1, 2) plt.plot(t, x_filtered) plt.title('Square Wave Signal After Passing Through a Lossy Channel') plt.xlabel('Time [s]') plt.ylabel('Amplitude') plt.grid(True) plt.tight_layout() plt.show() ``` Whose output is seen below:  > [!Figure] > *Attenuation losses for an input signal* Subtle things like surface roughness may also play a part in losses. To provide good adhesion between copper and dielectric materials in PCB core layers, PCB materials vendors control the roughness of the copper foil (typically by chemical treatment). Since the roughness is a random quantity, it is commonly specified in terms of the rms (root mean square) height, or $h$, of the surface unevenness. The surface roughness of the copper layers will not affect current at low frequencies because, at low frequencies, the depth of current penetration will exceed the value of height. Chemistry suppliers and foil manufacturers keep on researching ways of making copper smoother as there is a trade-off between achieving sufficient adhesion and ensuring reliability.  > [!Figure] > *Insertion loss (attenuation) considering surface roughness. Credit: Polar Instruments.* #### How much attenuation is too much attenuation? A rough estimation of attenuation per unit of length for FR4 material is given roughly by the next formula: $\large A\ \lbrack dB/in\rbrack\ = \ \frac{1}{w\ \lbrack mils\rbrack}\sqrt{f\ \lbrack GHz\rbrack} + 2.3\ x\ f\lbrack GHz\rbrack\ x\ D_{f}\text{\ x\ }\sqrt{D_{k}}$ For 1GHz, this gives roughly 0.3dB/in (0.2 dB/in from the conductor and 0.1 dB/inch from the dielectric). That is roughly 0.12dB/cm. In terms of how much attenuation if too much attenuation, an empirical rule of thumb says that attenuation beyond -8dB will collapse the eye beyond remedy and introduce unacceptable inter-symbol interference. These figures will help us quickly quantify the maximum length could reach for a specific Nyquist frequency to keep attenuation below the -8dB level. For instance, for an 8Gbps signal (4GHz Nyquist), the formula above gives 0.9dB/in, so if we want to keep our attenuation below -8 or -9 dB, our interconnect can be a maximum of 10 inches long, or 25.4 centimeters. It is still possible to recover an eye for attenuations beyond -8dB but it will require [[Physical Layer#Equalization|equalization]] of the channel. With best design practices and equalization, eyes can be reopened with as much as -15dB of attenuation. In extreme cases and using combined types of equalization, interconnects with as much as -25 dB of attenuation can be recovered, which means that with only 5% of the signal arriving at the receiver, it can still be recovered. Attenuations beyond -25 dB are practically unrecoverable. A somewhat less cost-effective design "knob" is, of course, to use higher quality dielectrics with lower dielectric constants like Megtron6^[https://api.pim.na.industrial.panasonic.com/file_stream/main/fileversion/9310]. ### Equalization ==Equalization is fundamentally about processing the signals to compensate for the undesired effects introduced by flawed interconnects.== Picture a perfect, short-rise time signal launched into an interconnect. In the frequency domain, if one has a very short rise time signal, then the spectrum looks like an ideal square wave, with frequency components dropping off inversely with frequency. If we sent this signal through an interconnect whose attenuation was constant with frequency, the spectrum would be the same coming out; there would be no rise time degradation. There would be no inter-symbol interference either, no leakage of information from one bit to the next if we could preserve the spectrum at the receiver. The problem is, as we discussed: that's not the way real interconnects behave. Real interconnects have a frequency-dependent attenuation. ==The problem is all about the geometry of the interconnect and about the material properties. Losses will impose the maximum length one can go given a desired bit rate for given losses.== For a receiver, an idea signal must complete a transition within a symbol interval. However, when the signal travels through an interconnect such as a lossy backplane, the transition expands to adjacent intervals. This is, again, inter-symbol interference (ISI). All things equal, there is one design trick one can add to compensate for all these challenges, and that is equalization. Equalization is performed using equalizers, which are electronic devices or digital algorithms designed to correct or mitigate the impairments that a signal undergoes while traversing a communication channel. Some standard high-speed digital interfaces like [[High-Speed Standard Serial Interfaces#PCI Express|PCI Express]]], USB 3.1, and Gigabit [[High-Speed Standard Serial Interfaces#Ethernet|Ethernet]] require equalizers in their physical layers. Also, transceivers inside modern [[Semiconductors#Field Programmable Gate Arrays (FPGA)|FPGAs]] are equipped with this functionality. ==In many of these standards, transmitters and receivers automatically negotiate the optimal equalization parameters.== The process of equalization can be done at either the transmitter side, the receiver side, or both, depending on the specific requirements of the system. It is important to highlight that equalization is only possible when the transmitters and/or receivers are capable of modifying the time-domain or frequency-domain features of their signals. Equalization also improves jitter due to ISI (see figure below).  > [!Figure] > *Jitter improvement with equalization (Source: https://people.engr.tamu.edu/spalermo/ecen689/lecture10_ee720_jitter.pdf)*  > [!Figure] > *Transmit pre-emphasis pre-distorts signals (source: https://blog.teledynelecroy.com/2018/06/introduction-to-channel-equalization.html)* One type of equalization is transmit pre-emphasis, in which the transmitted signal is modified (pre-distorted) by boosting high-frequency transitions relative to low-frequency transitions to compensate for the adverse effects of the channel. Pre-emphasis comes in two flavors: pre-shoot and de-emphasis. The purpose of pre-emphasis is to apply delay and inversion to the signal and add it back to the original signal with the proper weight, thereby compensating for the "expansion" or ISI from the nearby data symbol. Depending on the channel characteristics, one simple delay, inversion, and weight process may not be enough to achieve compensation. To achieve optimal channel loss compensation, designers can combine different delays, weights, and polarity in one pre-emphasis setup. Therefore, a real pre-emphasis implementation generally works like a [[Semiconductors#Microprocessor Devices#Digital Signal Processing#Filtering and Discrete-Time Fourier Transform (DTFT)|finite impulse response (FIR) filter]] with different "taps" that refer to signals after different unit delays.  > [!Figure] > _ISI Compensation with Pre-Emphasis (source: https://cdrdv2-public.intel.com/654771/an602.pdf_ After the signal traverses the channel, there are three types of equalization at the receiver: feedforward equalization (FFE), continuous time linear equalization (CTLE), and decision feedback equalization (DFE). Linear filtering at the receiver, accomplished either as a low-pass filter in CTLE or by using an FIR filter, boosts the signal's high-frequency content. DFE is a non-linear filter that also boosts high frequencies but does so after the detector or "slicer" (see second figure down below).  > [!Figure] > _Transmitted signal with and without emphasis (source: https://blog.teledynelecroy.com/2018/06/introduction-to-channel-equalization.html)_ We will see each one of these techniques next.  > [!Figure] > _Typical equalization architectures (Source: "Overview of Channel Equalization Techniques for Serial Interfaces" by Siemens)_ ##### Transmitter Emphasis In the frequency domain, the effect of equalization can be explained as a technique that counters the low-pass frequency response of the interconnect. ==Ideally, the transfer function of the equalizer should be the inverse of the transmission line transfer function such that the combined responses result in a flat line from DC up to a frequency equal to the Nyquist frequency.== One can use the pre-emphasis term if the channel loss is compensated by boosting the high-frequency content of the signal and de-emphasis if the compensation is done by decreasing its low-frequency content.  > [!Figure] > _Equalization in the frequency domain (Source: \"Overview of Channel Equalization Techniques for Serial Interfaces" by Siemens)_ In the time domain, pre-emphasis or de-emphasis indicates whether the amplitude of the emphasized signal is larger or smaller than the amplitude of the non-emphasized signal. This terminology is exemplified in the figure below.  > [!Figure] > _Transmitter pre- and de-emphasis (Source: "Overview of Channel Equalization Techniques for Serial Interfaces" by Siemens)_ The process to generate a differential pre-emphasis signal is rather straightforward, and depicted in the figure below. The original positive-leg signal Vp(t) is compared with the unit-delayed positive-leg signal Vp(t-1). Assuming the pre-emphasis weight is x (with 0<x<1), the difference between the Vp(t) signal and the weighted x\*Vp(t-1) signal is the emphasized signal (positive-leg). The negative leg of the emphasized signal is similarly generated. The pre-emphasized differential signal is differentiated from the positive-leg and negative-leg signals.  > [!Figure] > _Pre-emphasis signal generation (source: https://cdrdv2-public.intel.com/654771/an602.pdf)_ Considering that the peak-to-peak amplitude of the non-emphasized waveform is V, in the case of pre-emphasis, the peaking signal is added to the original waveform resulting in greater peak-to-peak signal amplitude. As opposed to that, in the case of de-emphasis, the peak-to-peak amplitude is maintained the same as that of the non-emphasized waveform (V), and the shoulder portion is suppressed from the original signal. Since the peaking duration is fixed and is triggered by the transitioning bits only, transmitter emphasis does not scale with the signal's data rate, and it becomes less efficient when deviating from the targeted data rate. The figure below shows the eye diagram of a PRBS-7 pattern after a lossy channel without pre-emphasis (shown on the left) and with certain pre-emphasis taps (shown on the right). The significant difference between the two eyes demonstrates how pre-emphasis can improve signal integrity through the lossy channel. As there is no free lunch, there are some disadvantages of pre-emphasis. Pre-emphasis increases the signal edge rate, which increases the crosstalk on the neighboring channels. Meanwhile, because pre-emphasis emphasizes the transition bits and de-emphasizes the remaining bits, if there is any discontinuity along the channel, the reflection at the discontinuity is more complicated than without pre-emphasis. Because the impact of pre-emphasis on crosstalk and channel discontinuity is highly case-dependent, simulation is required to ensure the impact is minimal.  > [!Figure] > _Eye Diagram of Data Pattern without Taps and with Taps (source: https://cdrdv2-public.intel.com/654771/an602.pdf)_ We will see next an example to demonstrate transmitter emphasis. In this example, we'll: - Create a simple digital signal. - Apply TX FIR equalization to the signal. This equalization is achieved by convolving the signal with an FIR filter, where the coefficients of the filter are set to achieve the desired equalization. - Simulate a basic channel effect (e.g., a low-pass filter) to show how the channel impacts the signal. - Display the original signal, the equalized signal, and the signal after it has passed through the channel. The code is as follows: ```python import numpy as np import matplotlib.pyplot as plt from scipy.signal import lfilter, butter, convolve # Function to generate a simple digital signal def generate_signal(length, repeat_factor): bit_sequence = np.random.choice([0, 1], size=length) return np.repeat(bit_sequence, repeat_factor) # Repeat bits for visibility # Low-pass filter to simulate channel loss def low_pass_filter(signal, cutoff_freq, fs, order=5): nyquist = 0.5 * fs normal_cutoff = cutoff_freq / nyquist b, a = butter(order, normal_cutoff, btype='low', analog=False) return lfilter(b, a, signal) # TX FIR equalization function def tx_fir_equalization(signal, fir_coefficients): return convolve(signal, fir_coefficients, mode='same') # Parameters fs = 1000 # Sampling frequency cutoff_low_pass = 100 # Low-pass cutoff frequency fir_coefficients = np.array([1, -0.5]) # FIR coefficients for TX FIR equalization signal_length = 100 # Length of the bit sequence repeat_factor = 10 # To make bits visible in the plot # Generate the signal signal = generate_signal(signal_length, repeat_factor) # Apply TX FIR equalization equalized_signal = tx_fir_equalization(signal, fir_coefficients) # Simulate the signal passing through a channel channel_affected_signal = low_pass_filter(equalized_signal, cutoff_low_pass, fs) # Plotting plt.figure(figsize=(15, 5)) # Original Signal plt.subplot(1, 3, 1) plt.plot(signal) plt.title('Original Signal') # Signal after TX FIR Equalization plt.subplot(1, 3, 2) plt.plot(equalized_signal) plt.title('After TX FIR Equalization') # Signal after passing through the Channel plt.subplot(1, 3, 3) plt.plot(channel_affected_signal) plt.title('After Channel (Low-pass filter)') plt.tight_layout() plt.show() ``` Which yields:  > [!Figure] > _TX Pre-emphasis Equalization example_ ##### Transmitter FIR equalization To generate the signal described in the section above, the most common transmitter equalization architecture is based on a digital FIR filter that is synchronized to the clock. A generic block diagram of a transmitter FIR equalizer is shown below.  > [!Figure] > _Transmitter FIR equalizer signal flowchart (source: "Overview of Channel Equalization Techniques for Serial Interfaces" by Siemens)_ Samples of the incoming data stream flow through a set of delay elements, represented as blue squares in the block diagram shown above. Those elements can be implemented in hardware with [[Semiconductors#Flip-Flops|flip-flops]] or shift registers and are usually referred to as the taps of the filter. The delay from one tap of the filter to the adjacent tap is known as tap spacing and usually is one unit interval (UI). In some cases, fractional spacing of the taps is also allowed. The taps of the filter are scaled, at each stage, by a tap weight value or a filter tap coefficient $C_i$ with $i$ being the tap index. The scaling is done with multipliers that are represented with green circles in the block diagram of the filter. The resulting signals are summed, in the red circle block, and sent to the data output. A filter with a high enough number of taps can reduce or even eliminate the system's ISI if the tap coefficients are carefully chosen. The simplest transmitter equalization architecture is used in links running at relatively low speed by today's standards. For example, PCIe Gen 1 (2.5Gbps), PCIe Gen 2 (5Gbps), and USB3.1 Gen 1 (5Gbps) specifications define a two-tap FIR filter with fixed equalization levels. ##### Receiver Continuous Time Linear Equalizer (CTLE) The equalization architecture of the serial protocols operating at data rates above 5/8Gbps usually includes a Continuous Time Linear Equalizer (CTLE) block situated on the receiver side. As opposed to FIRs which are discrete devices, CTLEs are analog circuits that are operating continuously and have the characteristics of a high-pass filter. They can be implemented in real hardware either using passive components or using active components. Instead of amplifying the high-frequency components of the signal, passive CTLEs attenuate the low-frequency components. Active CTLEs might provide some signal gain. Most of the CTLE architectures that are described in the serial protocol specifications are implemented with passive components integrated into the silicon. However, the filter can be located anywhere in the channel and can even be built into cables or connectors. CTLE, in combination with other equalization blocks like DFE, can improve the quality of the received signal in a way that is not possible with DFE alone. ##### Decision Feedback Equalizer (DFE) Serial interfaces running at 8Gbps and above usually include a Decision Feedback Equalizer (DFE) in their equalization architectures. The DFE is a non-linear equalizer, typically placed after the CTLE, and uses the previously detected symbols to estimate and cancel the post cursor's ISI from the input bit stream. As shown in the figure below, at a high level, the architecture of a behavioral DFE is very similar to that of a transmitter FIR. However, in this case, the filter is placed in a feedback loop together with a decision function (slicer). Similarly, to transmitter FIR, the DFE requires a clock to operate.  > [!Figure] > _Block diagram of a generic DFE with n taps (source: "Overview of Channel Equalization Techniques for Serial Interfaces" by Siemens)_ The decision function determines if the incoming signal is a "0" or a "1". The output of the slicer is fed into the FIR filter, where it gets multiplied by the filter's tap coefficients. The sum of the weighted and delayed signals is then subtracted from the input serial data. The tap coefficients are calculated based on the ISI introduced by the lossy interconnect and based on the previous decision, therefore a DFE can only cancel postcursor ISI. If the tap coefficients are properly chosen, the filter can remove as many taps of ISI as the DFE has. However, if any of the previous decisions are not correct, it is fed back to the input of the FIR and can generate error propagation. The number of DFE taps and the values of their coefficients affect the length of the error burst. Many hardware implementations are described in the literature. Each of them has its own merits and is more suitable for a particular application. However, from an educational perspective, two simple architectures are of interest: direct and speculative.  > [!Figure] > _Direct DFE architecture (source: "Overview of Channel Equalization Techniques for Serial Interfaces" by Siemens)_ The main element in the direct implementation is a latch with a sample threshold controlled by an analog block. The threshold can move up or down depending on the value of the previously received bit, in a similar fashion to Schmitt triggers. Although conceptually simple, this architecture suffers from the very narrow constraints imposed on the critical timing path. The feedback loop latency must be less than the bit period, which is a tough constraint for high data rate serial protocols. The second architecture is called "speculative" (or "unrolled") DFE architecture and is illustrated in the figure below.  > [!Figure] > _Speculative DFE architecture (source: \"Overview of Channel Equalization Techniques for Serial Interfaces" by Siemens)_ This architecture eliminates the critical timing constraints by duplicating the signal path. The path at the top uses the positive value of the tap coefficient, while the one at the bottom is a negative value. Then, a [[Semiconductors#Multiplexers and Demultiplexers|multiplexer]] selects the correct output depending on the value of the previously received bit. ##### Receiver Feed-forward Equalizer (FFE) The concept of digital Rx FFE is similar to that of the Tx FIR equalization block except for the addition of the analog-to-digital converter (ADC) that is needed at the input of the filter to deal with the analog nature of the signal. As for Tx FIR, the Rx FFE needs to be synchronized with the system's clock. Consequently, for proper operation, either the clock needs to be recovered at Rx, or the operating frequency must be known.  > [!Figure] > _Block diagram of a receiver digital FFE equalizer (source: "Overview of Channel Equalization Techniques for Serial Interfaces" by Siemens)_ From a functional perspective, the Tx FIR and Rx FFE produce similar results as long as they are identically configured. ##### Adaptive Equalization: Backchannel Backchannel capability, also called "link training" in the context of serial links, is the ability of the serial link receiver to automatically tune the equalization settings of the serial link transmitter to optimize signal integrity and bit error rate. This capability exists in serial link standards such as 10GBASE-KR, and PCI Express Gen3 and 4. Backchannel produces better BER margins than just the transmitter or the receiver being optimized individually, which is important as margins tighten up at higher data rates. In the way backchannel is implemented, the transmitter and receiver enter a training mode in which the transmitter is open to suggestions from the receiver as to how to adjust its equalization settings. During backchannel training, the transmitter sends a test pattern to the receiver. The receiver then evaluates the signal quality of the transmitted signals and communicates back through the physical channel (i.e., backchannel) to the transmitter, telling it how to adjust its equalization settings. The settings are adjusted, a new pattern is sent to the receiver for evaluation, and the process continues until either the receiver is satisfied with the signal quality, or the time or cycle limit is reached for the training process. When the transmitter's equalization settings are locked in, then the actual data transmission occurs. This process is illustrated in the figure below.  > [!Figure] > _Backchannel process (source: "Backchannel Modeling and Simulation Using Recent Enhancements to the IBIS Standard", Cadence)_ ##### Summary Each of the previously described equalization techniques has its own merits and flaws. The following table contains a summary of the most important characteristics of the most commonly used equalization types. | **Equalization type** | **Advantages** | **Disadvantages** | | --------------------- | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | | **Tx FIR** | Immune to noise enhancement, can cancel ISI in pre-cursor and beyond filter span. | Has limited output power, attenuates low-frequencies, and amplifies crosstalk; a back channel is required for adaptation. | | **CTLE** | Cost-effective and simple to implement, active CTLE provides gain and equalization with low power and area overhead, long post-cursor reach, and does not require a backchannel for adaptation. | Equalization is limited to 1st order compensation, very sensitive to PVT and hard to tune, has no precursor cancellation, amplifies high-frequency noise and crosstalk, linearity can be challenging. | | **DFE** | Noise and crosstalk neutral does not require backchannel for adaptation. | Nonlinear, can only cancel postcursor ISI, error propagation, feedback loop latency with critical timing path, requires complex CDR design. | | **Rx FFE** | Does not have limited output power as Tx FIR, does not require backchannel for adaptation. | Amplifies noise, precision, and setting coefficients require adaptive algorithms. Tuning delays for analog implementations. | ### Cross Talk and Ground Bounce Just as James Clerk Maxwell explained in his equations, a displacement current will reveal itself whenever there is a changing electric field applied to the conducting plates of a capacitor. When a voltage is suddenly applied in an interconnect, the voltage wavefront, as it travels, will create a changing electric field with it which will create a displacement current between the signal and return conductor that propagates down the channel. ==Currents propagate as a signal-to-return path loop wavefront with a given direction of propagation and a given direction of circulation: a positive voltage will circulate from signal to return, whereas a negative voltage will circulate from return to signal.== ==Currents do not only have a direction of propagation and direction of circulation but also a geometry that they will choose for flowing in the return path: currents will flow in proximity to the signal path.== For DC, currents take the lowest resistance path; as frequency increases, the imaginary (inductive) component of impedance $Z$ (with $Z\ = \ \ R\ + \ j\omega L)$ will become more predominant. A rule of thumb says that, for any signals higher than 1MHz, the inductive part will rule, and the return current will take the path of least inductance[^20]. In a microstrip, that means right under the signal line, which represents the smaller loop inductance. Of all the different paths the current can take, the path of lowest loop inductance is when the return current path is as close, underneath the signal current as it can get. The current redistributes to be directly underneath the signal path to minimize the loop inductance. The figure below shows a simulation performed with a proprietary solver from IBM and published by Bruce Archambeault in the IEEE EMC Magazine in 2008[^21]. In this simulation, the redistribution begins between 1 kHz and 50 kHz and is complete by 1 MHz. For all currents on a circuit board above 1 MHz, the return current is always flowing directly underneath the signal path.  > [!Figure] > _Simulation of distribution of return current for different frequencies. Source: https://www.signalintegrityjournal.com/articles/1771-a-simple-demonstration-of-where-return-current-flows_ Ground bounce is the voltage created on the return conductor due to changing currents through the total inductance of the return path. It is the primary cause of switching noise and EMI problems. It needs two ingredients: - A discontinuity in the return path - Adjacent signals with overlapping return currents As discussed, high-frequency currents tend to flow along the path of least impedance on the conductor's surface, a phenomenon known as the skin effect. This causes the current to be concentrated on the surfaces of conductors, increasing resistance and causing the effective cross-sectional area for current flow to reduce as frequency rises. Of course, the return path for these high-frequency signals also tends to follow the path of least inductance, which ideally is directly beneath the signal trace on the ground or power plane in a phenomenon known as the proximity effect. Anything that we may do in the return path that could increase the inductance (changing its geometry or anything that would affect the current distribution in that conductor) will increase its impedance and therefore create a discontinuity. What is more, adjacent signals with overlapping return paths will generate crosstalk. To discuss crosstalk, we need to discuss fringe fields. Fringe fields are the electric and magnetic fields that extend from the edges of conductors or interconnects, such as PCB traces and cables. When a single-ended signal propagates along a transmission line, the ideal assumption is that the electromagnetic field exists only between the trace and its return path. However, in reality, the fields do not terminate abruptly at the boundaries of the conductors. Instead, they "fringe" out into the surrounding space. The existence of fringe fields has negative implications for signal integrity, as they can couple with adjacent conductors, leading to what is called crosstalk. Crosstalk is the unwanted coupling between signal paths that can result in noise and signal degradation. Since fringe fields represent a deviation from the ideal field distribution in an interconnect, they can affect the characteristic impedance of the line, potentially leading to reflections and signal distortion. ==If the aggressor's conductor current changes, the fringe field lines that go around a victim will also change. If the field lines around a victim line change, a voltage will be induced, and that voltage will drive a current on the victim's conductor; this is crosstalk.== How does one eliminate it? By eliminating fringe field lines. Simple in principle, but somewhat complex in practice. There are two ways of achieving that. One is distance: we must simply pull signal paths farther apart. The second way of managing fringe field lines is proximity to the return plane. The closer one can bring the return plane to the signal lines, the more it is going to confine the fringe fields in proximity, and the fewer of them are going to be spread outward.  > [!Figure] > _Crosstalk in an I2C bus (green: aggressor, yellow: victim) (Credit: Elliott Williams, Hackaday)_ Bringing the return plane near the signal is going to substantially reduce how far fringe field lines will extend out, and it will reduce the amount of adjacent noise. That is, in principle, great news, as it transpires as an easy way of controlling the amount of crosstalk. But because there is no free lunch in engineering, we know we must always pay a penalty. What's the downside of bringing the return path closer? We will alter the impedance. And that is the usual whack-a-mole game that must be played as engineers of digital systems. You whack over here, and we did a great job of reducing the crosstalk. Which is good news. But now this other mole popped up over here and we got too low impedance. And too low of an impedance means we may have [[#Reflections|reflections]] when the signal wavefront hits the discontinuity. Which one wins will depend on system requirements. If the system lives for crosstalk and one wants to have as low a crosstalk as possible, then we must adapt to live with a lower impedance. Note that everything that we have discussed in this section is strictly about single-ended interconnects. We will discuss [[#Differential Interconnects|differential interconnects]] soon. ##### Near-end Crosstalk (NEXT) and Far-end Crosstalk (FEXT) We said a few paragraphs above that as the aggressor's conductor current changes, the fringe field lines that go around a victim will also change. If the field lines around a victim line change, a voltage will be induced, and that voltage will drive a current on the victim's conductor. In fact, as the aggressor's wavefront propagates down the channel, as a signal pulse is launched in the interconnect, the noise induced into the victim line will also propagate, and it will do it in both directions: a portion will propagate to the front, and another portion will do it to the back. The near-end noise, called near-end crosstalk (NEXT), propagates backward. That is, toward the victim's source, taking a round trip time to reach said source. If we doubled the length of the line, the magnitude of this near-end crosstalk would stay the same because it's only about the coupled region between the lines (figure below). If the coupled region hasn't changed, the amount of noise coupling over doesn't change. Line length will only change the duration of the near-end noise due to the fact the round trip time will be longer.  > [!Figure] > _NEXT and FEXT coupling regions (source: https://resources.pcb.cadence.com/blog/deep-dive-into-near-end-crosstalk-next)_ For the forward-moving noise, the situation is rather different. Because the noise induced in the victim is moving along with the signal pulse, there is an equivalent "noise pulse" adding up as it travels along the signal wave, inducing noise in the victim. Then, the forward-end noise gets bigger and bigger; that means that the far-end noise magnitude gets bigger with line length. The noise at the near end has a different signature compared to the noise at the far end because of the direction of propagation of the signal and because the noise splits as it couples into the victim line. #### Rail collapse > [!warning] > This section is under #development ### Electromagnetic Interference (EMI) In an unshielded cable, the return path for the common mode signal can be less obvious compared to differential mode signals, where the return path is the opposite conductor of the pair. For common mode signals, the return path involves the surrounding environment and structures, including the earth ground. Here’s a detailed look at how this works: #### Return Path for Common Mode Signals 1. **Earth Ground:** - **Environmental Ground:** Common mode currents in unshielded cables often return to their source through the earth ground. The earth ground acts as a vast, conductive medium that can facilitate the return of common mode currents. This is particularly relevant in large systems or installations where the equipment and interconnects are grounded to a common earth ground. - **Building Ground:** In indoor environments, the building’s grounding system, including metal structures, conduits, and ground wires, provides a path for common mode currents. This network of grounded metal can act as the return path. 2. **Parasitic Capacitance:** - **Capacitive Coupling to Ground:** Unshielded cables have parasitic capacitance between the conductors and the surrounding ground. This capacitance allows common mode currents to couple to the ground, providing a return path through the capacitive coupling. - **Nearby Conductive Surfaces:** Any nearby conductive surfaces, such as metal enclosures, circuit board ground planes, or other grounded equipment, can serve as part of the return path via capacitive coupling. 1. **Impedance Pathways:** - **Leakage Paths:** Common mode currents can return through leakage paths in the system. This includes paths through insulation resistance or any unintended conductive paths between the cable conductors and the ground. - **Inductive Coupling:** Although less common, inductive coupling to nearby grounded conductors can also contribute to the return path for common mode currents. #### Example Scenario Consider an unshielded twisted pair (UTP) cable used for data transmission. If a common mode signal is present on both conductors: 1. **Common Mode Currents on Conductors:** The common mode signal induces currents that flow in the same direction on both conductors of the UTP cable. 2. **Return Path through Ground:** These currents seek a return path through the earth ground or building ground. They might couple capacitively to nearby grounded structures or directly to the earth if the system is grounded to it. 3. **Capacitive Coupling:** Parasitic capacitance between the cable and surrounding grounded structures facilitates the return of these common mode currents. 4. **Completing the Circuit:** The common mode current flows through the ground back to the source of the signal, completing the circuit. #### Implications for EMI The less defined and often higher impedance return path for common mode signals can lead to higher radiated energy compared to differential mode signals. The common mode currents can create electromagnetic fields that radiate into the environment, leading to EMI issues. #### Mitigation Strategies To mitigate the effects of common mode signals and their associated EMI in unshielded cables: - **Use of Common Mode Chokes:** Placing common mode chokes on the cable can help attenuate common mode currents, reducing the EMI. - **Proper Grounding:** Ensuring good grounding practices and minimizing ground impedance can provide a more defined and lower impedance return path for common mode currents. - **Cable Layout and Routing:** Keeping cables away from potential radiative structures and avoiding running them parallel to other cables can reduce capacitive and inductive coupling, minimizing EMI. In a shielded cable, the return path for common mode signals is more controlled and can significantly reduce electromagnetic interference (EMI). Shielded cables use a conductive layer (the shield) surrounding the inner conductors, which provides a more defined and effective return path for common mode currents. Here’s how this works: #### Return Path for Common Mode Signals in Shielded Cables 1. **Shield as the Return Path:** - **Conductive Shielding:** The shield (which can be a braided wire, foil, or a combination of both) acts as a conductive layer that surrounds the inner conductors. Common mode currents on the inner conductors induce currents in the shield, which provides a low-impedance return path. - **Direct Return Path:** The common mode currents flow on the shield and return directly to the ground reference or the source of the common mode signal through the shield. This helps contain the electromagnetic fields and prevents them from radiating into the environment. 2. **Grounding the Shield:** - **Single-Ended Grounding:** In some designs, the shield is grounded at one end only. This helps to avoid ground loops but may be less effective at high frequencies. - **Double-Ended Grounding:** For better high-frequency performance, the shield can be grounded at both ends. This creates a more continuous and effective return path for high-frequency common mode currents. 3. **Capacitive and Inductive Coupling Reduction:** - **Reduced Capacitive Coupling:** The shield acts as a barrier that reduces capacitive coupling between the inner conductors and external environments, minimizing the coupling of common mode currents to external structures. - **Reduced Inductive Coupling:** The presence of the shield also reduces inductive coupling with nearby conductive elements, further containing the common mode currents within the shielded cable. #### Example Scenario Consider a shielded twisted pair (STP) cable used for data transmission with a common mode signal present on both conductors: 1. **Common Mode Currents on Conductors:** The common mode signal induces currents that flow in the same direction on both conductors of the STP cable. 2. **Shield as the Return Path:** These currents induce corresponding currents in the shield. The shield provides a low-impedance path for these currents to return to the signal source or ground. 3. **Ground Connection:** If the shield is grounded at both ends, the common mode currents can flow through the shield and return to the source via the ground connections, minimizing EMI. #### Implications for EMI The shield effectively contains the electromagnetic fields generated by the common mode currents, preventing them from radiating into the environment and causing EMI. This is particularly important for maintaining signal integrity and preventing interference with other electronic devices. #### Mitigation Strategies for Shielded Cables While shielded cables inherently provide better control over common mode currents and EMI, proper implementation is crucial: - **Ensure Proper Shield Grounding:** Properly grounding the shield at one or both ends is essential. Grounding at both ends is generally more effective for high-frequency signals but should be done carefully to avoid ground loops. - **High-Quality Shielding:** Using high-quality shielding materials and ensuring complete coverage without gaps or breaks is important for maintaining the integrity of the shield. - **Cable Management:** Even with shielding, good cable management practices, such as avoiding sharp bends and keeping the shield intact, help maintain the effectiveness of the shield. #### Cables and EMC Tests If there were any common current on a cable, to return through the stray fringe fields between the entire cable and the floor, back to the chassis, it would radiate. In the most sensitive FCC part 15 test condition—for 88 MHz and below—in a class B test, the largest acceptable far field at 3 m from the product is 100 µV/m. This is an important number to remember. This means that if there is a larger field at 3m from the product than 100 µV/m, at 88 MHz, within the 120 kHz bandwidth of the FCC test, the product will fail EMC certification and not be allowed for sale in the US. Other countries have similar certification requirements. When the source of the radiation is from common currents on external cables such as those that connect to peripherals, using a “better” cable often has no impact at all on the radiated emissions. That’s because the common currents are flowing on the shield of the cable. Remarkably, it only takes 3 µA of common current flowing on the shield of a cable, 1 m long, to cause an FCC class B failure. This is another really important number to remember, and it’s a tiny amount of current. The most important driving voltage for these common currents that causes EMC failures is ground bounce in the connector attaching the cable to the chassis. Ground bounce is the voltage generated between two regions of the return path due to a changing current flowing through the total inductance of the return path. The total inductance of the return path is related to the total number of field lines around the conductor per amp of current flowing through it. When the dI/dt of the return current flows through the total inductance of the connector, it generates a voltage, and this voltage between the chassis and the cable’s shield is what drives the common currents on the cable, which results in an EMC failure. This is illustrated in the figure below. ![[Pasted image 20240610182822.png]] > [!Figure] > Illustration of how ground bounce in a connector can drive common currents on a cable and fail an EMC certification test (source: http://www.oh3ac.fi/Reduce%20EMI%20Problems%20Right%20Away.pdf). A coax cable will have no ground bounce because there is no external magnetic field around it. The signal current generates an external magnetic field composed of circular rings of field lines circulating in one direction. The return current, if symmetrical about the signal path, generates the identical rings of magnetic field around the cable, but circulating in the opposite direction. These two sets of magnetic field lines exactly cancel out and there is no external magnetic field. But suppose at the connector, the return current is not perfectly symmetrical about the signal current. Maybe there is a pigtail, maybe the clamshell is not well metalized, or maybe the connector only makes contact at one or two points to the chassis. Any asymmetry will mean the magnetic field lines from the signal current and return current will not perfectly cancel out. There will be some net magnetic field lines and this will result in some total inductance of the return path. In a typical 50 Ω coax cable, with a 1V signal, having a 1ns rise time, the signal and return current is about 1 V/50 Ω = 20 mA. Even if the asymmetry is so slight as to generate only 0.1 nH of total inductance around the return path of the connector, the ground bounce voltage generated would be: ![[Pasted image 20240610183053.png]] If the impedance the common current sees returning through all those fringe field lines is about 200Ω, this 2 mV of ground bounce voltage will drive I = 2 mV/200 Ω = 10 µA. Is this a lot or a little? Remember, it only takes 3 µA of common current to fail an EMC certification test. This ground bounce-driven current in the cable shield will cause an EMC failure. > [!warning] > This section is under #development ### Jitter Jitter refers to the variation in the timing of a signal's pulses. In a perfect digital signal, these pulses would occur at precisely regular intervals. However, due to various factors like frequency-dependent losses, reflections, crosstalk, and discontinuities in the transmission medium, the timing of these pulses can vary. This variation is known as jitter. Jitter leads to problems in the receiver's decision-making circuitry, resulting in the misinterpretation of a "1" as a "0" or vice versa, thereby causing bit errors. The Bit Error Rate (BER) is calculated by dividing the total number of errors by the number of bits sent. The Total Jitter (TJ) of a system is assessed based on BER. To fully grasp a system's performance, it's important to evaluate both the Total Jitter concerning BER and its jitter components. Categorizing the TJ into various types of jitter is useful for system design. For instance, an in-depth examination of these jitter components is key to determining which part of the system is responsible for the failure of the eye diagram to meet the horizontal eye mask standards. Jitter categorization (also called separation, or jitter tree) in high-speed digital interconnects is an important concept for understanding when "budgeting" jitter to comply with interconnect specifications. A simplistic categorization of jitter is as follows: - Random Jitter: Caused by thermal noise and other stochastic processes such as clock/oscillator source, and clock recovery circuits. It is unpredictable and has a Gaussian distribution. RJ is assumed to have zero mean value and can be characterized by the root mean square (rms[^22]) value, $\large \sigma_{\text{RJ}}$. The peak-to-peak value of RJ must be quoted at a given bit-error rate (BER). - Deterministic Jitter: This includes all non-random jitter components and can be further categorized into: - Data-Dependent Jitter (DDJ): Related to the interaction of the transmitted data with the characteristics of the interconnect. Long sequences of the same values and sudden transitions may cause data-dependent jitter, hence the importance of [[High-Speed Standard Serial Interfaces#PCS & PMA|scrambling]]. - Bounded Uncorrelated Jitter (BUJ): Independent of data patterns but bounded within certain limits. BUJ is not aligned in time with the data stream, and the most common source is crosstalk. Classified as uncorrelated due to being correlated to the aggressor signals and not the victim signal or data stream. While uncorrelated, still a bounded source with a quantifiable peak-to-peak value - Sinusoidal or Periodic Jitter (SJ or PJ): Occurs at regular intervals, often due to interference from periodic signals or clock sources. If a measurement were to observe the time transitions of a signal, in a short time (several seconds), a histogram would capture the most probable timing locations of data transitions. This histogram is also known as a jitter histogram. If the histogram is rescaled such that the integral is unity, it becomes a probability density function (PDF) of jitter (figure below).  > [!Figure] > _Categorization of jitter (source: https://people.engr.tamu.edu/spalermo/ecen689/lecture10_ee720_jitter.pdf)_  > [!Figure] > _Probability density functions of jitter (source: https://people.engr.tamu.edu/spalermo/ecen689/lecture10_ee720_jitter.pdf)_ Designers must check the interface's specs to understand what the maximum jitter is—defined as a percentage of the UI—for budgeting purposes. It is understood that the total jitter PDF is a convolution integral of the bounded deterministic jitter (DJ) and unbounded Gaussian random jitter (RJ). Because DJ is finite and bounded, the extremes of the jitter PDF must consist only of RJ Gaussian "tails". $\large \text{PDF}_{\text{TJ}}(t) = \ \text{PDF}_{\text{RJ}}(t)\ *\ \text{PDF}_{\text{DJ}}(t)$ Where: $\large \text{PDF}_{\text{DJ}}(t) = \ \text{PDF}_{\text{SJ}}(t)\ *\ \text{PDF}_{\text{DCD}}(t)\ *\ \text{PDF}_{\text{ISI}}(t)\ *\ \text{PDF}_{\text{BUJ}}(t)$ Thus, the $rms$ standard deviation of the Gaussian can be found from the least squares fitting of these tail regions. Extrapolation of the fit allows the determination of the probability density of data transition locations that are very rare and are not captured in the limited measurement time. Total Jitter (TJ) must be specified at a given bit-error rate, or BER. The relationship between total jitter and BER is quite direct: as jitter increases, the likelihood of bit errors also increases. This is because, in a high-speed signal, the timing of the pulse edges is critical for correctly interpreting the bits. If there is significant jitter, the eye collapses and the receiver might misinterpret the timing of the edges, leading to errors in bit interpretation. >[!note] What gives the Gaussian distribution its characteristic bell shape? Forget for a moment about math. Even before math was invented by us humans, certain things were still normally distributed, even though we didn't know it nor even had a name for it. If our pre-math ancestors had the chance to measure something and plot it in their caves—for instance, the weight of chicken eggs—in pre-they would still have gotten a bell curve as a result. The bell shape of the normal distribution can be understood through the concept of aggregate effects of numerous small, independent factors. When we measure something, numerous tiny, independent factors influence the result. These factors can include slight variations in the measurement tool, environmental conditions, or inherent variability in the thing being measured. Most of these small factors don't push the measurement extremely far from the average; they cause only small deviations. This is why most of our measurements will cluster around a central value (the mean). Also, there's usually no inherent bias towards overestimation or underestimation in these small factors. This symmetry in variation leads to a symmetrical distribution of measurements around the mean. As we move further away from this central value, the chances of a measurement occurring there decrease. It's less likely that many factors will all align to produce a measurement much larger or much smaller than the average. A physical analogy that helps visualize why this bell shape arises is the Galton Board. In this device, balls drop through a series of pins. Each pin the ball hits knocks it slightly left or right, randomly. The numerous, small, independent deflections (representing the random factors in measurement) result in most balls ending up near the center, with fewer and fewer reaching the extreme sides. This process creates a bell-shaped distribution at the bottom. It is what you inevitably get if you combine lots of little variations, each one independent from the last, and each one negligible when compared to the total. The explanation of why we can predict how the tiny balls will distribute is rather intuitive. When a ball hits a peg, there's a 50% chance for it to go left or right. So, for it to fall in the leftmost slot, it would have to go left every time. For it to fall in the middle, it has to go left and right the same number of times. The most likely scenario is that a ball will hit some amount to the left, and some to the right (without having a particular preference), so more balls end up in the center than on the edges. This creates a predictable distribution pattern marked by the dark line in the toy. All in all, when we manually measure something that is normally distributed (like heights of people, errors in measurement, random jitter, etc.), each measurement is influenced by a myriad of tiny, independent factors. The central limit theorem indicates that when these small effects are added up, they tend to produce a distribution that is normal (or bell-shaped), regardless of the individual distributions of those effects. The bell shape is therefore a natural outcome of the aggregation of many small, independent influences, each causing slight deviations from an average, with no systematic bias towards one direction or another. This aggregation naturally leads to more occurrences near the average and fewer as we move away from it, creating the characteristic bell-shaped curve. ==In short, the bell shape is what you inevitably get if you combine lots of little variations, each one independent from the last, and each one negligible when compared to the total.== The Gaussian distribution is mathematically defined by the function: $f\left( x \right) = \frac{1}{\sqrt{2\pi\sigma^{2}}}e^{- \frac{\left( x - \mu \right)^{2}}{2\sigma^{2}}}$ where $\mu$ is the mean, and $\sigma$ is the standard deviation. >![[image77.jpeg]] > >Now if you want to see something that resembles a Galton board making a person feel extremely unlucky, see this video below: > ><iframe src="https://embed.reddit.com/r/nevertellmetheodds/comments/1hsh582/bank_wins/?embed=true&amp;ref_source=embed&amp;ref=share&amp;utm_medium=widgets&amp;utm_source=embedv2&amp;utm_term=23&amp;utm_name=post_embed&amp;embed_host_url=https%3A%2F%2Fpublish.reddit.com%2Fembed" width="640" scrolling="no" allowfullscreen="true" sandbox="allow-scripts allow-same-origin allow-popups" allow="clipboard-read; clipboard-write" style="border: none; max-width: 100%; border-radius: 8px; display: block; margin: 0px auto;" height="740"></iframe> For simplicity, let's assume a standard Gaussian distribution where $\large \mu$ = 0 and $\large \sigma$ = 1. Here's the Python code to implement and plot this distribution: ```python import matplotlib.pyplot as plt import math # Gaussian distribution function def gaussian(x, mu=0, sigma=1): return (1 / math.sqrt(2 * math.pi * sigma ** 2)) * math.exp(- (x - mu) ** 2 / (2 * sigma ** 2)) # Generating values x_values = [x / 100.0 for x in range(-500, 500)] y_values = [gaussian(x) for x in x_values] # Plotting the Gaussian distribution plt.figure(figsize=(8, 4)) plt.plot(x_values, y_values, label='μ=0, σ=1') plt.title('Gaussian Distribution') plt.xlabel('x') plt.ylabel('Probability Density') plt.legend() plt.grid(True) plt.show() ``` Here is the plot of a standard Gaussian distribution, where the mean $\large \mu$ is 0 and the standard deviation $\large \sigma$ is 1. The distribution is symmetric around the mean, and it shows the characteristic bell-shaped curve of Gaussian distributions.  > [!Figure] > _Gaussian distribution_ ##### Bathtub curves (BERT scans) Bathtub curves (also referred to as "BERT scans") are usually created with bit error ratio testers (BERT). A BERT generates data to pass through a device under test (DUT) and then measures the transmitted data and compares for errors, thus determining the bit error ratio (BER). As the measurement location is swept across a unit interval (UI), a plot of BER as a function of the unit interval is constructed. This plot typically resembles a cross-section of a bathtub, thus the name "bathtub curve".  > [!Figure] > _Illustration of the relationship between eye diagram, jitter PDF, and bathtub curve. top) Eye diagram indicating data transition threshold. middle) Jitter PDF. bottom) Bathtub curves found from jitter PDF (thick line) (source: http://www.wavecrestsia.com/technical/bulletins/2004130A.pdf)_ By measuring and building bathtub curves, one can graphically extract the total jitter (TJ):  > [!Figure] > _Estimating total jitter at a BER of 10-12 from the bathtub (source: https://www.synopsys.com/photonic-solutions/product-applications/other-applications/measurement-total-jitter.html)_ ##### Jitter Budgeting with Dual Dirac Model Jitter budgeting in digital systems is typically done using the dual-Dirac model, which is universally accepted for its utility in quickly estimating total jitter defined at a bit error ratio, or TJ(BER), and for providing a mechanism for combining TJ(BER) from different network elements. It relies on the following assumptions, some of which we already discussed: - Jitter can be separated into random jitter (RJ) and deterministic jitter (DJ). - Random Jitter follows a Gaussian distribution and can be fully described in terms of a single relevant parameter, the $rms$ value of the RJ distribution or, equivalently, the standard deviations of the Gaussian distribution, $\large \sigma$. - Deterministic Jitter follows a finite, bounded distribution. - Deterministic Jitter follows a distribution formed by two Dirac-delta functions. The time-delay separation of the two delta functions gives the dual-Dirac model-dependent DJ. - Jitter is a stationary phenomenon. That is, a measurement of the jitter on a given system taken over an appropriate time interval will give the same result regardless of when that time interval is initiated. Then, we do the [[Semiconductors#Microprocessor Devices#Digital Signal Processing#Linear Time-Invariant Systems and the Convolution Sum|convolution]] between both jitters and, as per [[Semiconductors#Microprocessor Devices#Digital Signal Processing#Frequency-domain Representation of Sampling|sampling theory]], the random jitter distribution gets replicated (sampled) by the impulses of the deterministic jitter:  > [!Figure] > _Dual-Dirac model for approximating total jitter (TJ) at a BER (source: https://people.engr.tamu.edu/spalermo/ecen689/lecture10_ee720_jitter.pdf)_ The Dual Dirac model states that most of the deterministic jitter in a system can be captured by two main peaks or impulses. These impulses are represented by the two Dirac delta functions, which are mathematical constructs that can represent an infinitely narrow and high pulse at a specific point in time. In the context of jitter analysis, these delta functions are used to model significant, discrete shifts in the timing of signal transitions. The two delta functions are positioned at specific locations along the time axis, which correspond to the most significant deviations from the ideal timing of signal edges due to deterministic jitter sources. The precise positioning of these deltas is derived from analyzing the signal and identifying the timing offsets that most frequently occur or have the highest impact on the signal's integrity. By analyzing the signal and modeling the deterministic jitter as two primary impulses, the Dual Dirac model allows engineers to quantify the magnitude and impact of these jitter components. This is done by measuring the distance between the two Dirac deltas (which represent the extent of the deterministic jitter) and their relative strength or amplitude. In practice, tools that employ the Dual Dirac model use statistical methods and signal processing algorithms to fit the model to the measured jitter profile of a signal. This involves analyzing a large number of signal transitions to determine the characteristic timing offsets and applying the Dual Dirac model to estimate the contributions of deterministic jitter components. ## Differential Interconnects We will explore now differential channels. One way of thinking of differential pairs is to think of them as two independent transmission lines sharing a common return path. We will see soon that they might not be truly single-ended after all. ##### Differential and Common Signal Components Differential signals are created by combining two independent voltages together. By choreographing these two voltages in a very specific way, we manage to obtain differential signals. But that is not all we get when we combine two voltages; we also obtain an unwanted by-product of combining signals called a common signal. ==By definition, the differential signal between these two voltages is their difference, whereas the common signal component is their average.== Why do we care about these two components, the differential signal component, and the common signal component? These two signals have their own character. They propagate independently of each other across interconnects, and they see different impedance environments as they propagate. Differential signals and common signals do not interact with each other at all as they propagate. When the differential signal travels across the transmission line, the instantaneous impedance that this signal sees is called differential impedance. It should be noted that we never create a common signal in a differential design, on purpose. There are two important factors contributing to the common signal. First is the transistor output technology; in some circuit technologies, the common signal is about half of Vcc. The second factor contributing to the appearance of a common signal is mode conversion, which stems from the fact no differential pair is perfect and there are always asymmetries between the positive and negative lines in a pair; these asymmetries appear due to length difference, a loss difference, or even an impedance profile difference. ##### Differential Impedance and Coupling To analyze the differential impedance, we will first consider there is no coupling between the two transmission lines of the differential pair. To remove all coupling between the lines, we must pull these two interconnects farther apart. In this case, the two interconnects have their characteristic impedance—say, 50 ohms—therefore, the differential impedance with no coupling will be the sum of their characteristic impedances, that is, 100 ohms. If we bring the interconnects closer together, they will not be isolated anymore. They will influence each other, as there will be fringe field lines from each transmission line encircling the other one, creating the equivalent effect of a capacitance between them. As the differential signal will swing between states, there will be displacement current happening because of this capacitance. The effect of that displacement current will manifest as an extra current added to the single-ended current, therefore decreasing the differential impedance. When the coupling is strong, we cannot say that each transmission line in this differential duet is truly "single-ended" anymore, as they are being affected by the fellow line. Note that calculating the actual value of differential impedance for coupled planar interconnects like microstrips are hard to do manually, therefore a 2D solver is needed. The closer the transmission lines, the lower the differential impedance. Why would we want to bring them together anyway if it screws our differential impedance? In terms of PCB design, it's real estate (board space) which translates into a lower cost. If we still want to increase our differential impedance, we will need to play with the trace geometry, using narrower lines. It is possible to create curves of constant differential characteristic impedance for certain geometries where we can play with trace widths and closeness while keeping the impedance constant. No free lunch rule strikes again: it's never free to narrow PCB traces, as it increases [[#Losses|losses]].  > [!Figure] > _Two transmission lines can form a differential pair_ ##### Propagation of a differential signal If we injected a differential signal into our two parallel lines (let's assume no common signal for now), the voltage waves would both propagate in the exact same direction. Let's assume we swing from 0 to 1V in one line, and from 0 to -1V on the other one (a 2V peak-to-peak differential signal). The current wavefronts of both signals would also travel in the same direction. But the direction of circulation would be different: on one line, the current would go from signal to return, whereas it would circulate from return to signal on the other one. Again, the level of coupling between them would play a part. > [!warning] > This section is under #development ##### Why Using Differential Signaling? All modern digital communication interfaces like PCI Express, USB, and Ethernet use differential signaling in their physical layers. Why? In a nutshell, differential signaling represents less noise at the receiver. Additionally, using differential signals brings the possibility of using lower voltages, because the differential receiver only cares about the voltage difference between the two lines. Thus, small absolute voltage levels can be effectively used, as long as the differential voltage remains within the detection threshold of the receiver. This means one can use a smaller voltage at the transmitter and still get an acceptable signal-to-noise ratio at the receiver, as they do not need to swing from ground to a high voltage level; they only need to swing around a common-mode voltage in opposite directions, all this with the associated advantage of lower power consumption. Differential pairs offer better noise immunity because external noise sources tend to affect both lines of a differential pair in the same way. When the receiver calculates the difference between the two signals, the noise, being common to both, cancels out. The last little advantage is that they represent a solution to one of the huge problems in single-ended signals: discontinuities of the return path that generate [[#Cross Talk and Ground Bounce|ground bounce]]. By using differential signaling, and in the presence of a discontinuity in the return path, if we happen to make the return currents of the two lines overlap, they will cancel out, minimizing ground bounce. Why, then, differential signaling is so widely adopted? Succinctly, because: - It has a better noise margin. - It has a better noise immunity. - Lower voltages can be used, meaning lower power. - Interconnects are less sensitive to return path discontinuities. We will see in the following sections that differential interconnects come with a good dose of design challenges as data rates go high. ##### Mode Conversion Mode conversion occurs in differential pairs if there is any asymmetry between the two lines that form the differential pair. This could be a length difference or a difference in losses between the two. There are some problems associated with mode conversion. The first problem is that, if some of the differential signal gets converted into common signal, then the differential signal has lost some energy. How much energy can one tolerate to lose? And empiric rule of thumb says we could tolerate as much as -15 dB of mode conversion before the differential signal is distorted enough to have an impact. The second problem arises if this common signal is not terminated, and reflects back and forth inside the differential pair, potentially getting reconverted back into differential signal, creating differential noise and affecting our interconnect's eye. Terminating the common and differential signals substantially reduces this problem. The third problem arises if any of these common signals should make their way out of the system as radiated emissions, such as on unshielded twisted pairs. As some analysis shows[^23], it may take as little as 5µA of common current on a cable to radiate enough to fail an EMI compliance test. How much common signal voltage is required to generate 5µA of current on the cable? It depends on the impedance the common signal sees. Generally, this will be high since the cable is far from its return path (see section 0 for interconnects without an adjacent return path). If we use a rough estimate of 200 ohms for the common impedance on an external cable, it will only take a voltage of 200 ohms × 5µA = 1mV to drive enough common current to fail a certification test. If the differential signal launched onto the differential pair is on the order of 1V, it would only require 0.1% of this converted into common signal to drive enough common current to tank a certification test. This is a -60 dB ratio, a really small amount. ==An inescapable truth is that real interconnects always show an amount of mode conversion due to manufacturing variations between the two lines that form the differential pair.== ##### Line-to-Line Skew Differential pairs appear as a great alternative for several problems that single-ended interconnects have. But, of course, differential channels require us to deal with two signals instead of one. Therefore, the choreography of these two signals must be close to perfect if we want the channel to work consistently at very high speeds. We are slowly realizing that differential pairs are not a panacea and require quite some effort to work right. Another issue differential channels bring is line-to-line skew. Line-to-line skew refers to the difference in the propagation time of signals in the two conductors of a differential pair. Ideally, in a differential pair, both lines should carry identical signals but in opposite phases (true differential mode), and they should arrive at the destination at the exact same time. Not a femtosecond earlier or later. However, due to manufacturing imperfections, differences in the length of the lines, or variations in the dielectric material, one line might have a slightly different electrical length than the other, causing a time delay between the signals. This skew can degrade the performance of the differential pair, as the differential signal at the receiver end won't be perfectly aligned in time. This misalignment can collapse the eye, increase bit errors, and overall degrade the signal quality. >[!Info] >Of of the reasons to keep skew under control in differential pairs is to maintain low EMI. When electric fields no longer cancel from equal and opposite currents, common-mode EMI will become a serious problem To minimize skew, careful layout and design practices are employed. This includes ensuring equal lengths for both lines but also maintaining consistent impedance and spacing throughout the length of the differential pair. How much skew can an interconnect tolerate? The worst situation appears when there is no termination of the common signal. Any common signal generated is going to be free to rattle around the channel until it converts into a differential signal. A 10% UI skew will indeed visibly impact the eye. But is 10% UI too much? The interconnect specs our designs are trying to comply with will play a significant role in establishing the values to use and the limits of what is tolerable versus what is not.  > [!Figure] > _Line-to-line skew (top: minimal, middle: late, bottom: early)_ Most serial, differential interconnect specs contain information in terms of how much line-to-line skew receivers can tolerate. Many of them are written for the worst case, considering no termination, when a common signal is free to bounce on and about. Typically, specs allow from 10 to 15 % of the unit interval (UI) line-to-line skew. For instance, PCI Express Gen2 uses a 5Gbps data rate, which means 200 picosecond unit interval. The PCI spec defines a line-to-line skew of 10% UI, which is 20 picoseconds. If a design showed 26 picoseconds, it could still work, due to the fact the spec specifies worst-case scenarios. A design could have 40 picoseconds of line-to-line skew and still work fine. It's just if the design wants to show high confidence and not have to do more detailed simulation, then it must keep the line-to-line skew less than the roughly 10% UI the specs define. Skew specs in general specify scenarios to ensure ample design margins and avoid performing time-consuming, detailed analysis and complex simulations. Designers can choose to play boldly and relax some of those requirements, at the expense of having to simulate and test more. Length matching in cables or traces on a printed circuit board (PCB) is a technique used to reduce intra-pair skew. In practice, when designing PCBs or cables, if one trace or wire in a differential pair is shorter than the other, additional length is added to it through various techniques. In PCB design, this often involves adding serpentine bends or meanders to the shorter trace (see figures below). These are zigzag patterns that increase the length of the trace without significantly altering its overall routing (other length-matching patterns are accordion and trombone). The goal is to match the lengths as closely as possible, often within very tight tolerances, to ensure that the skew is minimized.  > [!Figure] > _Accordion length matching (source: https://resources.altium.com/p/length-matching-high-speed-signals-trombone-accordion-and-sawtooth-tuning)_  > [!Figure] > _Trombone length matching (source: https://resources.altium.com/p/length-matching-high-speed-signals-trombone-accordion-and-sawtooth-tuning)_ When discussing propagation of signals, a valid question pops up; do differential signals travel faster than common signals in interconnects? In terms of time delay, it's not just about whether the signal is of differential or common nature, but more fundamentally on how the interconnect is designed. As we discussed, differential signals are generally preferred in high-speed applications due to their noise immunity, but this doesn't inherently mean they always have a lower time delay. The actual delay is highly dependent on the physical and electrical characteristics of the channel. If the interconnect is designed optimally for differential signaling, the differential signal will likely experience a less effective delay. For instance, in microstrip interconnects, for traces running on the top or bottom layers carrying differential signals, said signals will interact both with the substrate and also with the air, due to the fringe lines connecting both conductors in the pair. Therefore, the effective dielectric constant seen by those signals will be lower compared to signals whose fringe lines will only interact with the substrate material, as is the case of common signals. In microstrips, differential signals will show lower time delay compared to common signals; S-parameters will frequently show that $SDD_{21}$ is lower than $SCC_{21}$. Skew can also happen in cables, where similar principles apply. If one conductor in a twisted pair is shorter, additional length can be added by adjusting the twisting or by adding small service loops. The process of minimizing skew requires careful planning and precision, as even small differences in length can cause significant skew at high frequencies. The design and manufacturing processes involve software tools to calculate and adjust lengths precisely. Additionally, maintaining consistent impedance and avoiding sharp bends or kinks in the traces or cables is important, as these can also affect signal timing and quality. ##### Fiber Weave Effect It is a known fact that [[Printed Circuit Boards|PCBs]] affect signal integrity. Fiber Weave Effect (FWE) skew is the term commonly used when a fiberglass-reinforced dielectric substrate causes intra-pair skew for traces of the same length. Since the dielectric material used in the printed circuit board (PCB) fabrication process is made up of glass yarns woven into cloth and impregnated with epoxy resin, it becomes non-homogenous. When a top trace is routed over an area of low resin fill glass weave for a portion of its length, it has a different propagation delay compared to the bottom trace routed over an area of high resin fill glass weave. The difference in delay is known as timing or phase skew. In interconnects using differential signaling with a pair of transmission lines of equal length, any timing skew between positive (D+) and negative (D-) signals will convert some of the differential signal into a common signal component. Ultimately, this results in eye collapse at the receiver and contributes to electromagnetic interference (EMI).  > [!Figure] > _Timing skew due to FWE (source: https://www.signalintegrityjournal.com/articles/2459-beware-of-the-skew-budget-how-fiber-weave-effect-can-affect-your-high-speed-design)_ Timing skew in the time domain manifests itself as a resonant null in the frequency domain of the insertion loss ($SDD_{21}$, or how much signal goes through the interconnect and reaches the end of the line), as shown in the figure above. In this example, if the timing skew is equal to one-half unit interval (UI) of the baud rate, D+ and D- signals are shifted 90 degrees and the resonant null occurs at the frequency of the baud rate. If the intra-pair timing skew $t_{\text{skew}}$ and FWE lengths are known, the resonant frequency $f_{0}$ can be calculated using the following equation: $\large f_{0} = \ \frac{1}{2\ t_{\text{skew}}\ \text{length}_{\text{FWE}}} = \ \frac{1}{2\text{TD}_{\text{skew}}}$ where: $\large t_{\text{skew}}\ = \ \frac{\sqrt{\text{Dk}_{\max}} - \sqrt{\text{Dk}_{\min}}}{c}$ (given in seconds per unit length) $\text{length}_{\text{FWE}}$ = maximum FWE length $c$ = speed of light = 2.998E8 m/s $\text{Dk}_{\min}$, $\text{Dk}_{\max}$ are the minimum and maximum effective Dk due to the glass weave. When $\text{TD}_{\text{skew}}$ is equal to 1UI, D+, and D- signals are shifted 180 degrees and become in phase with one another. The resonant null occurs at the Nyquist frequency, equal to one-half of the baud rate, and the eye is totally closed.  $\large f_{0} = \ \frac{1}{2UI} = \ \frac{\text{Baud}}{2}\ = \ Nyquist\ frequency$ By definition, the baud rate is the number of symbols transmitted per UI. For non-return-to-zero (NRZ), the baud rate equals the symbol or bit rate. For pulse amplitude modulated 4-level (PAM-4) signaling, there are two symbols per UI and the baud rate is one-half the bit rate. So, for 56Gbps PAM-4, the baud rate is 28GBaud. The skew issue is exacerbated for PAM-4 signaling (figure below). In these examples, a simulated lossless transmission line is used to show the effect of eye closure due to skew.  > [!Figure] > _The effect of FWE skew on a lossless transmission line_ As we know, there is no such thing as a lossless transmission line, but it is a useful method to isolate loss strictly due to skew. As shown in the figure above (legend a), with 0UI of skew, the channel insertion loss is flat, and eyes are wide open; all signal goes through. A resonant null in the frequency domain, due to FWE skew, behaves like a notch filter. Depending on the Q-factor, frequencies near resonance are attenuated. If the resonant null occurs near the Nyquist frequency, the eye is reduced. In the example of the figure above (legend b), with 0.5 UI, there is a resonant null at the baud rate and the insertion loss is 3 dB at the Nyquist frequency. This causes an eye height (EH) reduction—the signal gets harmonics attenuated—and a subsequent increase in jitter. When the skew is 1UI as shown in the figure above (legend c), the resonant null is right at the Nyquist frequency, and the eyes are completely closed, due to the fact the fundamental of the signal is attenuated. With a lossy channel and other impairments, eye closure will only get worse. Designers must budget the total skew allowed for a given specification and tune the design to achieve that goal. Since FWE is a function of constructive factors such as glass weave style, resin chemistries, trace geometries, and stack-up parameters only to name a few things, it is difficult to establish a quantitative approach from data sheets. For bit rates above 25 Gbps, a 0.2 UI total skew budget can be insufficient for PAM-4 signaling for some industry standards. To mitigate the effect of skew on EH (Eye Height) and EW (Eye Width), a rule of thumb proposes that 0.14 UI be used for a total skew budget to maintain a channel bandwidth of at least seven times the Nyquist frequency of the baud rate. ##### Differential Pairs and Adjacent Return Planes (or the lack thereof) In planar interconnects, when there is an adjacent return plane, the properties of the differential pairs are dominated by the coupling between the signal conductors and their adjacent return path; there is very little overlap between return currents as every return current stays packed closed to its signal conductor. When the return path is not an adjacent plane (for instance in a twisted pair, connector, vias, sockets, or packages) the properties of differential pairs are rather different. For instance, in unshielded twisted pair cable, like Cat5 cable, the return path is a complicated structure composed of the fringe fields to the chassis, to the adjacent wires in the cable, and to any nearby conducting surface, which is usually the floor. In this case, with such a non-uniform return path, the return currents will combine and cancel out. Thus, all the properties the differential signal sees will be related to the coupling between the two signal conductors. In summary: - When a differential pair has an adjacent return plane in its vicinity, the properties of that pair are given by the interaction of each signal conductor and its return plane. - When a differential pair does not have an adjacent return plane, the properties of the pair are strictly given by the coupling between the two signal conductors. Board-level differential pairs are very different than differential pairs in unshielded twisted pairs. Note that the common signal does not follow the same logic because currents in a non-adjacent return path will not cancel out. Adding shielding to twisted pair cables (like CAT6 cables) does not change the situation for differential signals (the shield is still far enough to be considered non-adjacent). However, the shield will help to provide proximity for the common signal and help reduce radiated interference. ## Parallel versus Serial Interconnects ==Parallel and serial transmission are two methods for sending data over a communication channel, each with its unique characteristics and applications.== In parallel transmission, multiple bits are transmitted simultaneously, each over its own separate wire. For example, a single-ended, 8-bit parallel transmission would use eight separate wires, with each wire carrying one bit of the data simultaneously. This method is akin to traveling on a multi-lane highway where each lane carries a different part of the traffic simultaneously. Parallel transmission is often used in situations where distance is short, such as within a computer system (like between the CPU and RAM) or inside System-on-chips. However, the drawback is that it requires more wires, which can make the system more complex and expensive. It should also be clear by now that, at high speeds and over longer distances, parallel transmission will suffer severe [[#Signal Integrity|signal integrity]] issues like crosstalk. Moreover, parallel buses require a single, common clock source to synchronize transactions. Problems like length mismatch may cause the signal clock not to be uniform for all lines in the parallel bus, creating issues with setup and hold times, which are the times the signals must be stable in the bus to be sampled and interpreted. ==Serial transmission, on the other hand, sends data one bit at a time over a single wire or channel==. This is like a single-lane road where bits move in a queue. Examples of low-speed serial interfaces include 1-Wire, [[#I2C|I2C]], and [[#SPI|SPI]]]; all used for inter-chip communication on the same board. Also, [[#CAN|CAN]] is widely used for connecting several engine control units (ECUs) (engine control units) in automotive architectures but is also increasingly used in space avionics. High-speed serial interfaces, like PCI Express, Gigabit Ethernet, SerialRapid IO, USB, or SATA, are also serial and use more advanced techniques to transmit data at high rates over serial lines. We discuss [[High-Speed Standard Serial Interfaces|more]] about these interfaces later on. ### Link/Lane aggregation and Channel Bonding One can get the best of both worlds—that is, the concurrent nature of parallel channels with the robustness of differential serial channels—by parallelizing serial links. By combining several differential pairs in parallel carrying serial bit streams, and by orchestrating how the data is orchestrated as it is transferred in each lane, one can boost data throughput. In PCIe, the protocol orchestrates the transmission of data bytes across different lanes (see figures below).  > [!Figure] > _Transmission of encoded bytes through a 1-lane serial link. Source: PCI Express specification_  > [!Figure] > _Transmission of encoded bytes through a 4-lane aggregated serial link. Source: PCI Express specification_ Link/Lane aggregation is a way of keeping symbol rates of individual differential channels within manageable limits in terms of Nyquist frequencies and signal integrity without pushing the electrical limits of channels beyond practical boundaries. Therefore, when analyzing high-speed data interfaces, the data rate by itself is seldom a representative quantity in terms of the frequencies of the signals involved. It will largely depend on the signaling and the link aggregation strategy the protocol uses. When link aggregation is used, incoming streams originate from different transceivers and therefore they must be aligned. This process is commonly referred to as _channel bonding_. Channel bonding absorbs the skew between two or more multi-gigabit transceivers and presents the data to the user as if it were transmitted over a single link. The figure below illustrates the process.  > [!Figure] > _Channel bonding block diagram_ There are several causes of data skew between multiple transceivers: - Differences in transmission path length - Active repeaters in the transmission path - Differences because of clock correction - Differences in time to lock/byte alignment Since channel bonding requires communication and coordination between transceivers, the exact details will vary from vendor to vendor. Some common traits are the designation of one channel as the master channel, the designation of slaves, and possibly the designation of forwarding slaves. Three-level channel bonding that includes a master and forwarding slaves is sometimes referred to as two-hop channel bonding. It should be noted that link aggregation comes with the obvious penalty of increased wiring complexity, which also means higher mass. Therefore, aggregated links are not ideal for applications where weight reduction is king, for instance, aerospace and electric vehicles, where single-pair protocols are more popular. ## Bussed Interconnects ==A bussed interface is an interconnection topology where multiple components or devices are hooked to a common set of electrical lines, known as a _bus_==. A bus typically consists of wires or traces that carry signals that all nodes in the bus can interpret. Buses can run inside [[Semiconductors#System-on-Chips|System-on-Chips]] or microprocessors, on a PCB board, or connect several boards in a [[Backplanes and Standard Form Factors|backplane]]. In a bussed interface, each component connected to the bus can communicate with other components over the shared lines, depending on their role (in a single-master architecture, typically slaves are not able to directly talk to other slaves or initiate transactions). Buses tend to simplify the wiring and connectivity between multiple devices, as each device does not require a direct and individual connection to every other device. Instead, they all tap into the same set of shared lines. There can be parallel buses and serial buses. Parallel buses will share a higher amount of lines compared with serial buses. Examples of parallel buses are the classic PCI, ISA, or [[Backplanes and Standard Form Factors#VME|VME]]. Examples of low-speed, serial buses are I2C, SPI, and universal asynchronous receiver/transmitter (UART) using [[Physical Layer#TIA/EIA-422-B (RS422)|RS-422]] or RS-485 physical layers. One of the drawbacks of bussed interfaces is the need for arbitration; determining which device gets to use the bus when multiple devices need to communicate simultaneously. Various arbitration schemes can be used, like prioritizing devices by some criterion (for instance physical address) or using a controller or a master to orchestrate access to the shared bus. The advantages of a bussed interface include reduced complexity and cost because buses require fewer physical connections compared to other topologies like meshes. However, as the speed and number of devices on a bus increase, issues such as signal integrity, interference, and data collision become more pronounced. This has led to the development of more advanced communication protocols and bus systems, as well as a shift towards high-speed, point-to-point serial interfaces in many applications. ### I2C The I2C (pronounced I-squared-C) bus is a popular standard implemented in thousands of different chips manufactured by many companies. The I2C bus is used in various control architectures such as the System Management Bus (SMBus[^24]), Power Management Bus (PMBus[^25]), and [[Backplanes and Standard Form Factors#AdvancedTCA and MicroTCA|Advanced Telecom Computing Architecture (ATCA)]]. The popularity of I2C lies in the fact that, in low-complexity digital systems, there are often similarities between seemingly unrelated designs. For example, nearly every system includes: - A computing unit, usually a single-chip microcontroller - General-purpose elements like LCD and LED drivers, remote I/O ports, RAM, EEPROM, real-time clocks or analog-to-digital (A/D) and digital-to-analog (D/A) converters. To exploit these similarities to the benefit of both systems designers and equipment manufacturers, as well as to maximize hardware efficiency and circuit simplicity, Philips Semiconductors (now NXP Semiconductors) developed a simple bidirectional, single-ended 2-wire bus for inter-chip communications and control. This bus is called the Inter IC or I2C bus. All I2C-bus compatible devices incorporate an on-chip interface that allows them to communicate directly with each other via the I2C-bus. Here are some of the features of the I2C bus: - Only two bus single-ended lines are required: a serial data line (SDA) and a serial clock line (SCL). - Each device connected to the bus is software addressable by a unique address (usually defined by hardware), and simple controller/target relationships exist at all times; controllers can operate as controller-transmitters or as controller-receivers. - It is a true multi-controller bus including collision detection and arbitration to prevent data corruption if two or more controllers simultaneously initiate data transfer. - Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in the Standard mode, up to 400 kbit/s in the Fast mode, up to 1 Mbps in Fast mode Plus, or up to 3.4 Mbps in the High-speed mode. Serial, 8-bit oriented, unidirectional data transfers up to 5Mbps in ultra-fast mode are possible as per the specification. - On-chip filtering rejects spikes on the bus data line to preserve data integrity. - The number of ICs that can be connected to the same bus is limited only by the maximum bus capacitance. A typical application of I2C is depicted in the figure below.  > [!Figure] > _I2C typical application (source: https://www.nxp.com/docs/en/user-guide/UM10204.pdf)_ ##### Transactions I2C is a signal-based protocol, and as such, it defines a set of signal conditions that are relevant to how the bus operates. In I2C, the data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (see figure below). One clock pulse is generated for each data bit transferred.  > [!Figure] > _Bit transfer in an I2C bus_ All I2C transactions begin with a START (S) condition and are terminated by a STOP (P). A HIGH to LOW transition on the SDA line, while SCL is HIGH, defines a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (see figure below).  > [!Figure] > _I2C start and stop conditions_ START and STOP conditions are always generated by the controller. The bus is considered to be busy after the START condition. The bus is considered to be free again at a certain time after the STOP condition. The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this respect, the START (S) and repeated START (Sr) conditions are functionally identical. Detection of START and STOP conditions by devices connected to the bus is easy if they incorporate the necessary interfacing hardware. However, devices with no such interface have to sample the SDA line at least twice per clock period to sense the transition. Every byte put on the SDA line must be eight bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte must be followed by an Acknowledge bit. Data is transferred with the Most Significant Bit (MSB) first (see below). If a target cannot receive or transmit another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the clock line SCL LOW to force the controller into a wait state. Data transfer then continues when the target is ready for another byte of data and releases clock line SCL.  > [!Figure] > _Data transfer on the I2C bus_ The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal to the transmitter that the byte was successfully received, and another byte may be sent. The controller generates all clock pulses, including the acknowledge ninth clock pulse. The Acknowledge signal is defined as follows: the transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse. Set-up and hold times must also be considered. When SDA remains HIGH during this ninth clock pulse, this is defined as the Not Acknowledge signal. The controller can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer. Five conditions lead to the generation of a NACK: 1. No receiver is present on the bus with the transmitted address so there is no device to respond with an acknowledge. 2. The receiver is unable to receive or transmit because it is performing some real-time function and is not ready to start communication with the controller. 3. During the transfer, the receiver gets data or commands that it does not understand. 4. During the transfer, the receiver cannot receive any more data bytes. 5. A controller-receiver must signal the end of the transfer to the target transmitter. Two controllers can begin transmitting on a free bus at the same time and there must be a method for deciding which takes control of the bus and complete its transmission. This is done by clock synchronization and arbitration. In single-controller systems, clock synchronization and arbitration are not needed. Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCL line. This means that a HIGH to LOW transition on the SCL line causes the controllers concerned to start counting off their LOW period and, once a controller clock has gone LOW, it holds the SCL line in that state until the clock HIGH state is reached (see figure below). However, if another clock is still within its LOW period, the LOW to HIGH transition of this clock may not change the state of the SCL line. The SCL line is therefore held LOW by the controller with the longest LOW period. Controllers with shorter LOW periods enter a HIGH wait state during this time.  > [!Figure] > _Clock synchronization during the arbitration procedure_ When all controllers concerned have counted off their LOW period, the clock line is released and goes HIGH. There is then no difference between the controller clocks and the state of the SCL line, and all the controllers start counting their HIGH periods. The first controller to complete its HIGH period pulls the SCL line LOW again. In this way, a synchronized SCL clock is generated with its LOW period determined by the controller with the longest clock LOW period, and its HIGH period determined by the one with the shortest clock HIGH period. Arbitration, like synchronization, refers to a portion of the protocol required only if more than one controller is used in the system. Targets are not involved in the arbitration procedure. A controller may start a transfer only if the bus is free. Two controllers may generate a START condition within the minimum hold time of the START condition which results in a valid START condition on the bus. Arbitration is then required to determine which controller will complete its transmission. Arbitration proceeds bit by bit. During every bit, while SCL is HIGH, each controller checks to see if the SDA level matches what it has sent. This process may take many bits. Two controllers can complete an entire transaction without error, as long as the transmissions are identical. The first time a controller tries to send a HIGH, but detects that the SDA level is LOW, the controller knows that it has lost the arbitration and turns off its SDA output driver. The other controller goes on to complete its transaction. No information is lost during the arbitration process. A controller that loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration and must restart its transaction when the bus is free. If a controller also incorporates a target function and it loses arbitration during the addressing stage, the winning controller may be trying to address it. The losing controller must therefore switch over immediately to its target mode. The figure below shows the arbitration procedure for two controllers. More may be involved depending on how many controllers are connected to the bus. The moment there is a difference between the internal data level of the controller generating DATA1 and the actual level on the SDA line, the DATA1 output is switched off. This does not affect the data transfer initiated by the winning controller.  > [!Figure] > _Arbitration procedure for two controllers_ Since control of the I2C bus is decided solely on the address and data sent by competing controllers, there is no central controller, nor any order of priority on the bus. There is an undefined condition if the arbitration procedure is still in progress at the moment when one controller sends a repeated START or a STOP condition while the other controller is still sending data. In other words, the following combinations result in an undefined condition: - Controller 1 sends a repeated START condition and controller 2 sends a data bit. - Controller 1 sends a STOP condition and controller 2 sends a data bit. - Controller 1 sends a repeated START condition and Controller 2 sends a STOP condition. ### SPI A Serial Peripheral Interface (SPI) system consists of one master device and one or more slave devices. The master is defined as (typically) a microcontroller providing the SPI clock and the slave as any integrated circuit receiving the SPI clock from the master. The SPI uses a single-ended, 4-wire synchronous serial interface. Data communication is enabled with a low active Slave Select or Chip Select wire (CSB). Data is transmitted with a 3-wire interface consisting of wires for serial data input (MOSI), serial data output (MISO), and serial clock (SCK). SPI, due to its simplicity, finds application as short-distance, inter-chip communication typically within the boundaries of the same PCB board, although this is not strictly required, and certain architectures may employ SPI for inter-board communication. The figure below depicts a typical application of the SPI bus.  > [!Figure] > _SPI typical application_ In SPI, each transmission starts with a falling edge of the chip select signal (CS) and ends with a rising edge of it. During transmission, commands and data are controlled by SCK and chip select according to the following rules: - Commands and data are shifted; MSB first, LSB last. - Each output data/status bits are shifted out on the falling edge of SCK (MISO line) - Each bit is sampled on the rising edge of SCK (MOSI line) - After the device is selected with the falling edge of the chip select, an 8-bit command is received. The command defines the operations to be performed. - The rising edge of CS ends all data transfer and resets the internal counter and command register. - If an invalid command is received, no data is shifted into the chip and the MISO remains in a high impedance state until the falling edge of CS. This reinitializes the serial communication. - Data transfer to MOSI continues immediately after receiving the command in all cases where data is to be written to ASIC's internal registers. - Data transfer out from MISO starts with the falling edge of SCK immediately after the last bit of the SPI command is sampled in on the rising edge of SCK - The maximum SPI clock frequency is 500kHz.  > [!Figure] > _Data transmission in SPI bus_ ### CAN The Controller Area Network (CAN) protocol, developed by ROBERT BOSCH GmbH, aims to offer a solution to managing communication between multiple microcontrollers. CAN Specification 2.0 (September 1991) added an extended message format that increases the number of permitted message identifiers. CAN Specification 2.0 is 100% backward compatible with the previous CAN Specification 1.2. The ISO 11898 standard  > [!Figure] > _The layered implementation of CAN, as per ISO 11898_ The CAN communication protocol is a carrier-sense, multiple-access protocol with collision detection and arbitration on message priority (CSMA/CD+AMP). CSMA means that each node on a bus must wait for a prescribed period of inactivity before attempting to send a message. CD+AMP means that collisions are resolved through a bit-wise arbitration, based on a pre-programmed priority of each message in the identifier field of a message. The higher priority identifier always wins bus access. That is, the last logic high in the identifier keeps on transmitting because it is the highest priority. Since every node on a bus takes part in writing every bit "as it is being written" an arbitrating node knows if it placed the logic-high bit on the bus. The ISO-11898:2003 Standard, with the standard 11-bit identifier, provides for signaling rates from 125 kbps to 1 Mbps. The standard was later amended with the "extended" 29-bit identifier. Bus access is event-driven and takes place randomly. If two nodes try to occupy the bus simultaneously, access is implemented with a non-destructive, bit-wise arbitration. Non-destructive means that the node winning arbitration just carries on with the message, without the message being destroyed or corrupted by another node. The allocation of priority to messages in the identifier is a feature of CAN that makes it particularly attractive for use within a real-time control environment. The lower the binary message identifier number, the higher its priority. An identifier consisting entirely of zeros is the highest priority message on a network because it holds the bus dominant the longest. Therefore, if two nodes begin to transmit simultaneously, the node that sends a last identifier bit as a zero (dominant) while the other nodes send a one (recessive) retains control of the CAN bus and goes on to complete its message. A dominant bit always overwrites a recessive bit on a CAN bus. Note that a transmitting node constantly monitors each bit of its own transmission. The propagation delay of a signal in the internal loop from the driver input to the receiver output is typically used as a qualitative measure of a CAN transceiver. This propagation delay is referred to as the loop time but takes on varied nomenclature from vendor to vendor. Figure 2‑85 displays the CAN arbitration process that is handled automatically by a CAN controller. Because each node continuously monitors its own transmissions, as node B's recessive bit is overwritten by node C's higher priority dominant bit, B detects that the bus state does not match the bit that it transmitted. Therefore, node B halts transmission while node C continues on with its message. Another attempt to transmit the message is made by node B once the bus is released by node C. This functionality is part of the ISO 11898 physical signaling layer, which means that it is contained entirely within the CAN controller and is completely transparent to the user.  > [!Figure] > _A CAN Bus with three nodes_  > [!Figure] > _Arbitration on a CAN bus_ The allocation of message priority is up to the system designer, but industry groups mutually agree on the significance of certain messages. For example, a manufacturer of motor drives may specify that message 0010 is a winding current feedback signal from a motor on a CAN network and that 0011 is the tachometer speed. Because 0010 has the lowest binary identifier, messages relating to current values always have a higher priority on the bus than those concerned with tachometer readings. > [!info] > To be #expanded ### Data Rate vs Distance When we discussed [[#Signal Integrity|signal integrity]], and in particular when we discussed [[#Losses|losses]], we saw that interconnects behave like low pass filters, and this affects the rise time of our signals because harmonics necessary for the signal "sharpness" get attenuated along the way. Then, if we want a signal to propagate through longer distances at a given rate, we have a few design "knobs" to tweak: - We can make our [[#Losses|losses]] and [[#Reflections|reflections]] better (this is difficult because it depends on constructive aspects like surface roughness and materials and also on better impedance matching, better simulation, etc). - We can boost our signals to overcome the adverse frequency response of the channel using more sophisticated [[#Equalization|equalization]] techniques. - We can alter the signaling method and voltage swings to improve noise margins. - Or we can simply decrease our signaling rate to relax our unit intervals and keep our eye patterns open. The last option may appear as the most "boring" option (it feels like accepting defeat), but it is a valid strategy, depending on the application. Some applications do not require fast data transfer but reliable transmission of data across a given distance. The figure below shows the relationship between the signaling rate and the maximum distance to achieve reliable communication, for different signaling standards. When transmission distance increases, standards with higher voltage swings or differential signaling perform better. If data transmission over about 30m and less than 50 Mbps is required, differential signaling standards TIA/EIA-422 and TIA/EIA-485 must be considered. High differential outputs, sensitive receivers, and the capability to operate with up to 7 V of ground noise make these interfaces ideal for long direct connections between equipment. TIA/EIA-422 and TIA/EIA-485 use similar voltage levels but differ in the bus topologies they can support. TIA/EIA-422 is used for multidrop (one driver and many receivers) operation, while TIA/EIA-485 allows for multipoint signaling (many drivers and receivers).  > [!Figure] > _Approximate Signaling Rate vs Transmission Distance for Various Interfaces_ Increasing voltages will not go "unpaid". The penalty is power consumption. The figure below shows the power comparison for different signaling standards. We discuss some of these standards in the next subsection.  > [!Figure] > _Load power comparison for differential interfaces_ #### TIA/EIA-644A (LVDS) LVDS (Low Voltage Differential Signaling) is currently standardized by the TIA/EIA (Telecommunications Industry Association/Electronic Industries Association) ANSI/TIA/EIA-644-A (LVDS) Standard The generic (multi-application) LVDS standard, ANSI/TIA/EIA-644-A, began in the TIA Data Transmission Interface committee TR30.2 in 1995. It was revised and published as ANSI/TIA/EIA-644-A in 2001. The ANSI/TIA/EIA standard defines driver output and receiver input characteristics; thus, it is an electrical-only standard. It does not include functional specifications, protocols, or even cable characteristics since these are application-dependent. ANSI/TIA/EIA-644-A is intended to be referenced by other standards that specify the complete interface (i.e., connectors, protocol). This allows it to be easily adopted into many applications. The LVDS interface is intended for use where any of the following conditions prevail: - The data signaling rate is too high for effective unbalanced (single-ended) operation. - The data signaling rate exceeds the capability of TIA/EIA-422 or TIA/EIA-485 (differential) electrical interfaces - The balanced interconnecting media is exposed to extraneous noise sources that may cause an unwanted voltage of up to ±1 V measured differentially between the signal conductor and circuit common at the load end of the cable. - It is necessary to minimize electromagnetic emissions and interference with other signals. The LVDS interface circuit will normally be utilized on data and timing, or control circuits. The actual maximum data signaling rate is NOT defined by the specification. The limit is determined by the generator transition time characteristics, the media characteristics, the distance between the transmitter (or *generator* in LVDS jargon) the load, and the required signal quality. ==A theoretical maximum limit is calculated at 1.923Gbps and is derived from a calculation of signal transition time at the load assuming a loss-less balanced interconnect.== The recommended signal transition time ($t_{\text{rise}}$ or $t_{\text{fall}}$) at the load should not exceed 0.5 of the unit interval to preserve signal quality. ===The LVDS standard specifies that the transition time of the generator into a test load be 260ps or slower. Therefore, with the fastest generator transition time, a loss-less balanced interconnect, and applying the 0.5 restriction, this yields a minimum unit interval of 520ps or 1.923 Gbps theoretical maximum data signaling rate.=== A recommended maximum data signaling rate is derived from a calculation of signal transition time at the load. For example, if a cable media is selected, a maximum signal rise time degradation is assumed to be 500ps, since cables are not loss-less (500ps represents a typical amount of rise time distortion on 5 meters of cable). Therefore, allowing a 500ps degradation of the signal in the interconnecting cable yields a 760ps (fastest) signal at the load. Therefore, with the fastest generator transition time, and a cable with only 500ps of signal degradation (transition time), and applying the 0.5 restriction, yields a minimum unit interval of 1.520ns or 655Mbps recommended maximum data signaling rate based on this set of assumptions. The maximum data signaling rate is thus application-dependent. LVDS is a low-voltage signaling standard. An LVDS output driver provides 350 mV, nominal, into a 100-Ω load. This results in roughly 1.2 mW of power delivered to the load. The figure above compares the load power of LVDS compared with other differential signaling techniques and shows LVDS to be 1.5% to 50% of the presented signaling approaches. ##### Electrical Characteristics An LVDS interface circuit is shown in the figure below. The circuit consists of three parts: the generator (G) or transmitter, the balanced interconnect, and the load. The load is composed of a termination impedance and receiver(s) (R). A receiver may incorporate the termination impedance internal to a device package. The electrical characteristics of the transmitter and receiver are specified in terms of direct electrical measurements while the balanced interconnecting media is described in terms of its electrical characteristics.  > [!Figure] > _LVDS interface circuit_ Legend: G = Generator R = Receiver A = Generator interface point A' = Receiver interface point B = Generator interface point B' = Receiver interface point C = Generator circuit common C' = Receiver circuit common ZT = Termination impedance Vcpd = Common potential difference  > [!Figure] > _LVDS signaling at the transmitter_ During transitions of the transmitter's output between alternating binary states, the differential voltage measured across the 99.8 ohm ±1% test load (RL) connected as shown in the figure above, shall be such that the voltage monotonically changes between 0.2 and 0.8 of VSS and is less than or equal to 0.3 of the unit interval. Then, the signal voltage shall not vary more than ±20% of the steady-state value (Vring in the figure below depicting the waveform), until the next binary transition occurs. Transition times shall not be less than 260ps. Edge rates less than 260ps are not recommended to minimize the adverse effects of switching noise.  > [!Figure] > _Test circuit for waveform measurement_ VSS is defined as the voltage difference between the two steady-state values of the transmitter output (VSS = 2|Vt|). See the figure below.  > [!Figure] > _LVDS waveform_ An LVDS-compliant transmitter must be capable of furnishing the signal necessary to drive multiple (up to 32) parallel-connected receivers (without internal termination). However, the physical arrangement of the multiple receivers involves consideration of stub line lengths, location of the termination resistor, number of receivers, data signaling rate, circuit common, etc., that may degrade the signal at the receivers if not properly implemented. The TIA/EIA 644 standard recommends that stub lengths off the main line be as short as possible. In general, the propagation delay of the stub, should not exceed 30% of the signal transition time to prevent reflections and severe impedance discontinuities. For applications with receivers without internal termination, the external termination resistor must be located at the far end (last receiver) of the interconnect. The LVDS interface circuit is not intended for direct inter-operation with other interface electrical characteristics such as TIA/EIA-422, or TIA/EIA-485. Under certain conditions, inter-operation with circuits of some of these interfaces may be possible but may require modification in the interface or within the equipment or may require limitations on certain parameters (such as common-signal range); therefore, a satisfactory operation is not assured, and additional provisions not specified in the standard may be required. LVDS is poised to become even more popular in the industry due to its benefits and forward compatibility with ever-decreasing power supply magnitudes. It is also friendly regarding EMI and power dissipation performance. The new flavors of LVDS extend its applicability even further into a wider range of applications. The future will bring even higher line speed capability and operation at lower voltages along with increased integration. ##### Flavors Today a wide variety of LVDS Interface devices are available from many suppliers worldwide. This includes simple PHY devices such as line drivers and receivers that convert between LVDS and LVTTL levels. These are available from single channels in very small packages up to many channels in one package. Serializer/Deserializer ([[Semiconductors#Field Programmable Gate Arrays (FPGA)#SerDes and High-Speed Transceivers|SerDes]]) devices are also popular as they unleash the LVDS's speed capability and offer good system benefits. SerDes collect many slow-speed, single-ended signals and serializes them into high-speed LVDS channels. The narrower LVDS interface saves connector pins and reduces the size and weight of connectors and cables, which both in turn reduce system costs. The receiver devices deserialize the LVDS signals and generate the wide TTL bus at the destination. The throughput of these parts is attractive, with chipsets delivering more than 5Gbps of bandwidth over only 9 pairs. The popularity of LVDS signaling is increasing every year. Many other application-specific devices are replacing power-hungry and noisy CMOS logic with LVDS. #### TIA/EIA-422-B (RS422) TIA/EIA-422-B (RS-422) is an industry-standard that specifies the electrical characteristics of a bussed interface circuit. RS-422 interfaces are implemented when single-ended interfaces, lacking common-mode noise rejection capabilities and with data rates usually limited to less than 0.5Mbps, cannot reliably perform in noisy environments. RS-422 interfaces appear as an alternative to overcome these limitations.  > [!Figure] > _Cable length vs data rate_ An RS-422 driver can drive up to ten unit loads (4kΩ to circuit common is one unit load). The driver is capable of transmitting data across 1.2 km (recommended limit) of cable; but not at maximum data rates (see figure above). Standard RS-422 drivers are assured to source and sink a minimum of 20mA across a 100-ohms load. This corresponds to a minimum differential output voltage, VOD, of 2V across the load, as per the figure below.  > [!Figure] > _Receiver operating range_ The complement RS-422 receiver must be equal to or less than one unit load. This is represented by the slope of the shaded region in the figure above. The operating range of the receiver is defined between ±10 V and is represented by the shaded area in the figure above. Termination is recommended for use when designing an RS-422 interface that is considered to be a transmission line. Transmission line characteristics may restrict the use of a multi-drop configuration and limit the maximum data rate of the RS-422 interface. ##### Typical Configurations For RS-422 interface devices, usually three types of configurations are commonly used. - Point-to-Point Configuration: point-to-point, is a one driver and one receiver system. Point-to-point applications may be thought of as using single-ended standards like TIA/EIA-232-E because this is the configuration single-ended standards are popular for. However, differential standards are not restricted from use in point-to-point applications. A typical point-to-point system is shown in the figure below.  - Multi-Drop Configuration: multi-drop involves one driver with two or more receivers normally connected in a daisy chain layout. For RS-422, the maximum number of receivers is 10 if the receiver's input impedance is equal to 4kΩ or one unit load. If a receiver's input impedance is equal to 8kΩ then that receiver is equal to ½ a unit load. Therefore, an RS-422 driver that can drive 10 unit loads can drive 20 receivers with a higher input impedance. An example of a multi-drop application is shown in the next figure.  - Multi-Point Configuration: The last type of configuration is multi-point, which uses two or more drivers connected to one or more receivers. RS-422 drivers are normally not designed into this type of configuration. However, a multi-point system can be accomplished if certain issues are addressed. The three issues are ground potential differences between drivers, contention between drivers, and the driving capability of the drivers. Therefore, RS-485 devices are recommended for multi-point applications. #### Single Ended Signaling: TTL, TIA/EIA-232-E We have been mentioning "single-ended" signaling without really explaining what it means. In single-ended signaling, the signal's electromagnetic field is referenced against a common conductor. This conductor acts as a return path for the electrical current and provides a stable reference point for the signal's voltage. When you measure the voltage of the signal, you're actually measuring the difference in electric potential between the signal wire and this ground. Since the signal is referenced to a common return conductor, any interference or noise introduced into the system can affect the signal's integrity. This noise can alter the perceived voltage level of the signal, leading to errors in the interpretation of the data being transmitted. Single-ended signals are still widely used in many applications due to their simplicity and cost-effectiveness, especially where the distances are short, and the environment is controlled to minimize noise. Examples include internal connections within chip dies, where the signals don't have to travel long distances and are relatively shielded from external noise. >[!info] >It is quite common to hear engineers use "single-ended" and "TTL" interchangeably, although these two terms refer to different things! TTL is a logic family, and it specifies voltage thresholds and currents related to chips implementing Transistor-transistor logic. For any logic family, there are several threshold voltage levels to know. Below is an example of standard 5V TTL levels: - VOH: Minimum OUTPUT Voltage level a TTL device must provide for a HIGH signal. - VIH: Minimum INPUT Voltage level to be considered a HIGH state. - VOL: Maximum OUTPUT Voltage level a device will provide for a LOW signal. - VIL: Maximum INPUT Voltage level to still be considered a LOW.  There are several versions of TTL, such as Low-Power Schottky TTL (LS-TTL), which introduced refinements to enhance performance while reducing power consumption. LS-TTL maintains similar voltage levels but achieves lower power dissipation and faster switching speeds through the use of Schottky diodes in its design. Furthermore, Advanced Schottky TTL (AS-TTL) further optimized TTL's performance by incorporating advanced semiconductor materials and fabrication techniques. AS-TTL exhibits even faster switching speeds and reduced power consumption compared to LS-TTL, making it suitable for high-speed applications demanding stringent performance criteria. Despite variations in performance characteristics, TTL logic families share the fundamental operational principles and voltage level specifications, ensuring compatibility across different TTL devices. This adherence to standardized voltage levels enables seamless integration and interoperability, fostering the widespread adoption of TTL technology in various digital systems and applications. ##### RS-232 The official name of the EIA/TIA-232-E standard is "Interface Between Data Terminal Equipment and Data Circuit-Termination Equipment Employing Serial Binary Data Interchange". The legacy RS232 standard is concerned with serial data communication between a host system (in the jargon, called Data Terminal Equipment, or DTE) and a peripheral system (called Data Circuit-Terminating Equipment, or DCE). An ancestor of serial interfaces, The EIA/TIA-232-E standard was introduced in 1962 and has since been updated four times to meet the evolving needs of serial communication applications. ###### RS-232 Specifications RS-232 is a complete standard. This means that the standard sets out to ensure compatibility between the host and peripheral systems by specifying: 1. Common voltage and signal levels 2. Common pin-wiring configurations 3. A minimal amount of control information between the host and peripheral systems. Unlike many standards that simply specify the electrical characteristics of a given interface, RS-232 specifies electrical, functional, and mechanical characteristics to meet the above three criteria. Each of these aspects of the RS-232 standard is discussed below. ###### Electrical Characteristics The electrical characteristics section of the RS-232 standard specifies voltage levels, rate of change for signal levels, and line impedance. As the original RS-232 standard was defined in 1962 and before the days of TTL logic, it is no surprise that the standard does not use 5V and ground logic levels. Instead, a high level for the driver output is defined as between +5V to +15V, and a low level for the driver output is defined as between -5V and -15V. The receiver logic levels were defined to provide a 2V noise margin. As such, a high level for the receiver is defined as between +3V to +15V, and a low level is between -3V to -15V. The figure below illustrates the logic levels defined by the RS-232 standard. It is necessary to note that, for RS-232 communication, a low level (-3V to -15V) is defined as a logic 1 and is historically referred to as "marking". Similarly, a high level (+3V to +15V) is defined as a logic 0 and is referred to as "spacing".  > [!Figure] > _RS-232 logic-level specifications (source: https://www.analog.com/en/resources/technical-articles/fundamentals-of-rs232-serial-communications.html)_ The RS-232 standard also limits the maximum slew rate at the driver output. This limitation was included to help reduce the likelihood of crosstalk between adjacent signals. With this in mind, the maximum slew rate allowed is 30V/ms. Additionally, the standard defines a maximum data rate of 20kbps, again to reduce the chance of crosstalk. The impedance of the interface between the driver and receiver has also been defined. The load seen by the driver is specified at 3kΩ to 7kΩ. In the original RS-232 standard, the cable length between the driver and receiver was specified to be 15 meters maximum. Revision "D" (EIA/TIA-232-D) changed this part of the standard. Instead of specifying the maximum length of cable, the standard specified a maximum capacitive load of 2500pF, clearly a more adequate specification. The maximum cable length is determined by the capacitance per unit length of the cable, which is provided in the cable specifications. The following table summarizes the electrical specifications in the current standard. | Cabling | Single-ended | | ------------------ | ------------------------------------------------------------------------- | | Number of Devices | 1 transmit, 1 receive | | Communication Mode | Full duplex | | Distance (max) | 50 feet at 19.2kbps | | Data Rate (max) | 1Mbps | | Signaling | Unbalanced | | Mark (data 1) | -5V (min) -15V (max) | | Space (data 0) | 5V (min) 15V (max) | | Input Level (min) | ±3V | | Output Current | 500mA (Note that the driver ICs normally used in PCs are limited to 10mA) | | Impedance | 5kΩ (Internal) | | Bus Architecture | Point-to-Point | ###### Functional Characteristics Because RS-232 is a complete standard, it includes more than just specifications on electrical characteristics. The standard also addresses the functional characteristics of the interface. This essentially means that RS-232 defines the function of the different signals used in the interface. These signals are divided into four different categories: common, data, control, and timing. The table below describes the signals and the directions. The standard provides many control signals and supports a primary and secondary communications channel. Few applications, if any, require all these defined signals. For example, only eight signals are used for a typical application. The complete list of defined signals is included here as a reference. | Circuit Name* | Circuit Direction | Circuit Type | | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | -------------------------------------------------------------------------------------------------------------------------------------------------------------------- | ------------ | | Signal Common | — | Common | | Transmitted Data (TD) <br>Received Data (RD) | To DCE <br>From DCE | Data | | Request to Send (RTS) <br>Clear to Send (CTS) <br>DCE Ready (DSR) <br>DTE Ready (DTR) <br>Ring Indicator (RI) <br>Received Line Signal Detector** (DCD) <br>Signal Quality Detector <br>Data Signal Rate Detector from DTE <br>Data Signal Rate Detector from DCE <br>Ready for Receiving <br>Remote Loopback <br>Local Loopback <br>Test Mode | To DCE <br>From DCE <br>From DCE <br>To DCE <br>From DCE <br>From DCE <br>From DCE <br>To DCE <br>From DCE <br>To DCE <br>To DCE <br>To DCE <br>From DCE | Control | | Transmitter Signal Element Timing from DTE | To DCE | | | Transmitter Signal Element Timing from DCE <br>Receiver Signal Element Timing from DCE | From DCE <br>From DCE | Timing | | Secondary Transmitted Data <br>Secondary Received Data | To DCE <br>From DCE | Data | | Secondary Request to Send <br>Secondary Clear to Send <br>Secondary Received Line Signal Detector | To DCE <br>From DCE <br>From DCE | Control | \*Signals with abbreviations in parentheses are the eight most commonly used signals. \*\*This signal is more commonly referred to as Data Carrier Detect (DCD). ###### Mechanical Interface Characteristics The third area covered by RS-232 is the mechanical interface. Specifically, the RS-232 standard specifies a 25-pin connector as the minimum connector size that can accommodate all the signals defined in the functional portion of the standard. The pin assignment for this connector is shown in the figure below. The connector for DCE equipment is male for the connector housing and female for the connection pins. Likewise, the DTE connector is a female housing with male connection pins. Although RS-232 specifies a 25-position connector, this connector is often not used. Most applications do not require all the defined signals, so a 25-pin connector is larger than necessary. Consequently, other connector types are commonly used. The most popular connector is the 9-position DB9 connector, also illustrated in the figure below, right hand. This 9-position connector provides, for example, the means to transmit and receive the necessary signals for an application.  > [!Figure] > _RS232 Connectors and Pin Assignment. Credit: ADI_ ###### Practical RS-232 Implementation Most systems designed today do not natively use RS-232 voltage levels. Consequently, level conversion is necessary to implement RS-232 communication. Level conversion is performed by special RS-232 ICs with both line drivers that generate the voltage levels required by RS-232, and line receivers that can receive RS-232 voltage levels without being damaged. These line drivers and receivers typically invert the signal as well, since a logic 1 is represented by a low voltage level for RS-232 communication, and a logic 0 is represented by a high logic level. The figure below illustrates the function of an RS-232 line driver/receiver in a typical application. In this example, the signals necessary for serial communication are generated and received by the Universal Asynchronous Receiver/Transmitter (UART) discrete chip, or by an internal UART peripheral in a microcontroller. The RS-232 line driver/receiver IC performs the level translation necessary between the CMOS/TTL and RS-232 interface.  > [!Figure] > _Typical RS-232 application, including level shifter. Credit: ADI_ The UART performs the "overhead" tasks necessary for asynchronous serial communication. Asynchronous communication usually requires, for example, that the host system initiate start and stop bits to indicate to the peripheral system when communication will start and stop. Parity bits are also often employed to ensure that the data sent has not been corrupted. The UART chip or peripheral usually generates the start, stop, and parity bits when transmitting data, and can detect communication errors upon receiving data. The UART also functions as the intermediary between byte-wide (parallel) and bit-wide (serial) communication; it converts a byte of data into a serial bit stream for transmitting and converts a serial bit stream into a byte of data when receiving. ###### RS-232 in Typical Applications In a typical RS-232 application, designers use 9-pin connectors. The "basic nine" signals used in a typical application are illustrated in the figure above; three RS-232 drivers and five receivers are necessary for the DTE. The functionality of these signals is described below. Note that for the following signal descriptions, ON refers to a high RS-232 voltage level (+5V to +15V), and OFF refers to a low RS-232 voltage level (-5V to -15V). Keep in mind that a high RS-232 voltage level actually represents a logic 0 and that a low RS-232 voltage level refers to a logic 1. **Transmitted Data (TD)**: One of two separate data signals, this signal is generated by the DTE and received by the DCE. **Received Data (RD)**: The second of two separate data signals, this signals is generated by the DCE and received by the DTE. **Request to Send (RTS)**: When the host system (DTE) is ready to transmit data to the peripheral system (DCE), RTS is turned ON. In simplex and duplex systems, this condition maintains the DCE in receive mode. In half-duplex systems, this condition maintains the DCE in receive mode and disables transmit mode. The OFF condition maintains the DCE in transmit mode. After RTS is asserted, the DCE must assert CTS before communication can commence. **Clear to Send (CTS)**: CTS is used along with RTS to provide handshaking between the DTE and the DCE. After the DCE sees an asserted RTS, it turns CTS ON when it is ready to begin communication. ###### RS-232 in Minimal Handshake Applications Although the typical application discussed above is simplified from the RS-232 standard because of the number of signals needed, it is still more complex than many system requirements. For many applications, only two data lines and two handshake control lines are necessary to establish and control communication between a host system and a peripheral system. For example, a control system may need to interface with a thermostat using a half-duplex communication scheme. At times the control systems read the temperature from the thermostat and at other times they load temperature set points to the thermostat. In this type of simple application, only five signals could be needed (two for data, two for handshake control, and ground). The figure below illustrates a simple half-duplex communication interface. As can be seen, data is transferred over the TD (Transmit Data) and RD (Receive Data) pins, and the RTS (Ready to Send) and CTS (Clear to Send) pins provide handshake control. RTS is driven by the DTE to control the direction of data. When it is asserted, the DTE is placed in transmit mode. When RTS is inhibited, the DTE is placed in receive mode. CTS, which is generated by the DCE, controls the flow of data. When asserted, data can flow. However, when CTS is inhibited, the transfer of data is interrupted. The transmission of data is halted until CTS is reasserted.  > [!Figure] > _Half-duplex communication scheme. Credit: ADI_ ###### RS-232 Limitations In the more than four decades since the RS-232 standard was introduced, the electronics industry has changed immensely. There are, therefore, limitations in the dated RS-232 standard. One limitation—the fact that over twenty signals have been defined by the standard—has already been addressed. Designers simply do not use all the signals or the 25-pin connector. Other limitations in the standard are not necessarily as easy to correct. Generation of RS-232 Voltage Levels: As explained in the **Electrical Characteristics** section, RS-232 does not use the conventional 0 and 5V levels implemented in TTL and CMOS designs. Drivers have to supply +5V to +15V for a logic 0 and -5V to -15V for a logic 1. This means that extra power supplies are needed to drive the RS-232 voltage levels. Typically, a +12V and a -12V power supply are used to drive the RS-232 outputs. This is a great inconvenience for systems that have no other requirements for these power supplies. With this in mind, RS-232 level shifters have on-chip charge-pump circuits that generate the necessary voltage levels for RS-232 communication. The first charge pump essentially doubles the standard +5V power supply to provide the voltage level necessary for driving a logic 0. A second charge pump inverts this voltage and provides the voltage level necessary for driving a logic 1. These two charge pumps allow the RS-232 interface products to operate from a single +5V supply. Maximum Data Rate: Another limitation of the RS-232 standard is the maximum data rate. The standard defines a maximum data rate of 20kbps, which is insanely slow for many of today's applications. RS-232 products manufactured by Dallas Semiconductor guarantee up to 250kbps and typically can communicate up to 350kbps. While providing a communication rate at this frequency, the devices still maintain a maximum 30V/ms slew rate to reduce the likelihood of crosstalk between adjacent signals. Maximum Cable Length: As we have seen, the cable-length specification once included in the RS-232 standard has been replaced by a maximum load-capacitance specification of 2500pF. To determine the total length of cable allowed, one must determine the total line capacitance. The total capacitance is approximated by the sum of the mutual capacitance between the signal conductors and the conductor to shield capacitance (or stray capacitance in the case of unshielded cable). As an example, assume that the user decided to use a non-shielded cable when interconnecting the equipment. The mutual capacitance (Cm) of the cable is found in the cable's specifications to be 20pF per foot. Assuming that the receiver's input capacitance is 20pF, this leaves the user with 2480pF for the interconnecting cable. From the equation in the figure below, the total capacitance per foot is 30pF. Dividing 2480pF by 30pF reveals that the maximum cable length is approximately 80 feet or 24 meters. If a longer cable length is required, the user must find a cable with a smaller mutual capacitance.  > [!Figure] > _Interface cable-capacitive model, per unit length. Credit: ADI_ ## Optical Channels Optical communications harness light to transmit information across distances. At its core, optical communication relies on light as a medium, as opposed to the more traditional transmission methods using electrical interconnects like copper which we discuss in other sections. Optical technology branches into two main categories, which we will discuss next: [[#Fiber Optic|fiber optic communications]] and [[#Free Space Optical Communication|free-space optical communications]], each with unique characteristics and applications. Fiber optic communications, a widely adopted form, uses thin strands of glass or plastic fibers to guide light signals over long distances. These fibers are designed to minimize loss and maintain the integrity of the light signal. Inside these fibers, light is kept in the core ensuring that light pulses, which carry data, travel long distances with minimal signal degradation. The capacity of fiber optics to handle vast amounts of data at high speeds has substantially shaped telecommunications, offering wider bandwidth and security. On the other hand, free-space optical communications, abbreviated FSO, transmits data through open air or vacuum, using light beams. This method doesn't require a physical medium like fiber cables, making it an attractive option for certain applications. FSO systems use lasers or LEDs to send optical signals directly through the air, making them ideal for a variety of ranges of communications from inter-buildings to satellites. While offering the advantage of rapid deployment and flexibility, FSO is more susceptible to atmospheric conditions. Factors like fog, rain, and dust can attenuate or scatter the light beams, potentially degrading communication. ### Fiber Optic After unpacking the challenges of transferring high-speed data using copper interconnects, fiber optic technology represents an attractive alternative. Although the fundamental principles still rely on James Clerk Maxwell's work, fiber optic cables use higher-frequency electromagnetic waves (light) to transmit data, which offers several distinct advantages. Every fiber optic system has three basic components: a source, a fiber, and a receiver. The fiber serves as a light waveguide in this case; its purpose is simply to convey light from the source to a desired destination. In optical communications systems, the source of light used is called a transmitter. There are different types of transmitters, including light-emitting diodes (LEDs) and various types of laser transmitters. Their purpose is to convert an electrical signal into an optical signal which can be guided by the fiber. This process is called modulating the source of light. For example, picture a flashlight being switched on and off very quickly; the pattern of optical pulses forms a signal that carries information, similar to the way a telegraph or Morse code system operates. Turning a light source on and off in this way is called, unsurprisingly, on/off modulation. Of course, there are less rudimentary approaches; the light can also be adjusted to different levels of brightness or intensity, rather than simply being turned on and off, this is called analog modulation. Some types of light sources cannot be easily turned on or off; in this case, the light source may be left on all the time, and another device called an external modulator is used to switch the beam on and off (analogous to a window shutter placed in front of a flashlight). The simplest type of modulation involves throttling the intensity or brightness of the light; this is known as amplitude modulation (analogous to AM modulation in electric signals). It is also possible to modulate other properties of the light, such as its phase, frequency, or even polarization; however, these are not as commonly used in communication systems. The fiber is a thin strand of glass or plastic that connects the light source to its destination (it connects the transmitter to the receiver). There are other ways to carry an optical signal without using fibers. For example, another type of optical waveguide can be made by layering polymers or other materials on a [[Printed Circuit Boards|printed circuit board]]; these waveguides work on the same basic principles as an optical fiber. If the distances are reasonably short, light can simply be directed through free space. This approach can be used between two buildings if they are not too far apart by using two telescopes or lenses aimed at each other, with a light source on one side and a detector or receiver on the other side. This requires an unobstructed line of sight between the transmitter and the receiver, as well as good alignment so that the beam does not miss the receiver; bad weather conditions will also affect how well this system works. The fiber often has layers of protective coatings applied to strengthen it and form an optical cable, in the same way that copper wires are often coated with plastic. Just as electrical connectors are required to plug a cable into a socket, optical connectors, and sockets are also needed. Both fiber and copper cables may also be spliced to increase the distance, although the process is more difficult for fiber than for most copper systems. Most fibers used today are made from extremely high-purity glass and require special fabrication processes. In an optical communication system, the light is delivered to an optical receiver, which performs the opposite function of the transmitter; it converts optical signals back to electrical signals in a communication system. A receiver is composed of an optical detector (sometimes called a photodetector) and its associated electronics. After traveling through the various components of a fiber optic link, the signal we are trying to detect will be corrupted by different types of noise sources. The receiver must be designed to separate a signal from this noise as much as possible. A simple approach would be to amplify the signal, and devices called repeaters and optical amplifiers may be inserted at various points along the link for this purpose. They can be used to extend the range of the system; however, bear in mind that amplification cannot solve all our problems, since it often increases the power of both the signal and the noise. Some types of noise cannot be overcome simply by increasing the signal strength (for example, [[#Jitter|jitter]] on the digital data bits in a communication system). In some applications a transmitter and receiver are packaged together; when this is the case, it is called a transceiver. Communication systems may also use other devices such as multiplexers, which combine several signals over the same optical fiber. Different wavelengths, or colors of light, can be carried at the same time over the same fiber without interfering with each other. This is called wavelength division multiplexing (WDM). Optical fibers are often interconnected to form large networks which may reach all around the world. According to sources, there are millions of kilometers of fiber optic laid out around the world. Trends are showing that, by combining the world's fiber-optic network with other communication technologies, like satellites, could create a low-cost global real-time monitoring network, changing the rules not only on how we communicate but also how we observe our planet. #### Fiber Optic Principles We can direct light from one point to another simply by shining it through the air. We often visualize light in this way, as a bundle of light rays traveling in a straight line; this is one of the most basic approaches to light, called geometric optics. It is certainly possible to send useful information in this way (imagine signal fires, smoke signals, or ship-to-shore lights), but this requires an unobstructed straight line of light, which is often not practical. Also, light beams tend to spread out as they travel (imagine a flashlight spot, which grows larger as we move the light further away from a wall). We could make the light turn corners using an arrangement of mirrors, but this is hardly comparable to the ease of running an electrical wire from one place to another. Also, mirrors are not perfect; whenever light reflects from a mirror, a small amount of light is lost. Too many reflections will make the optical signal too weak for us to detect. To fully take advantage of optical signaling, we need it to be at least as easy to use as a regular electrical wire and have the ability to travel long distances without significant loss. These are the principal advantages of an optical fiber. ==Instead of using mirrors, optical fibers guide light with limited loss by the process of total internal reflection.== To understand this, we need to know that light travels more slowly through transparent solids and liquids than through a vacuum, and travels at different speeds through different materials. The relative speed of light in a material compared with its speed in a vacuum is called the refractive index, $n$, of the material. For example, if a certain kind of glass has a refractive index of 1.4, this means that light will travel through this glass 1.4 times more slowly than through vacuum. The bending of light rays when they pass from one material into another is called refraction and is caused by the change in refractive index between the two materials. The refractive index is a useful way to classify different types of optical materials; to give a few examples, water has a refractive index of about 1.33, most glass is around 1.5-1.7, and diamond is as high as 2.4. For now, we will ignore other factors that might affect the refractive index, such as changes in temperature. We can note, however, that the refractive index will be different for different wavelengths of light (to take an extreme example, visible light cannot penetrate your skin, but X-rays certainly can). At optical wavelengths, the variation of refractive index with wavelength is given by the Sellmeier equations. Total internal reflection is described by Snell's Law, given by Equation X, which relates the refractive index and the angle of incident light rays. This equation is illustrated by the figure below, which shows two slabs of glass with a ray of light entering from the lower slab to the upper slab. Here, $n_{1}$ is the index of refraction of the first medium, $\theta_{1}$ is the angle of incidence at the interface, $n_{2}$ is the index of refraction of the second medium, and $\theta_{2}$ is the angle in the second medium (also called the angle of refraction). Snell's Law states that: $\large n_{1}sin(\theta_{1})\ = \ {n_{2}\sin}{(\theta_{2})}$ Thus, we can see that a ray of light will be bent when it travels across the interface. Note that as we increase the angle $\theta_{1}$, the ray bends until it is parallel with the interface; if we continue increasing $\theta_{1}$, the light is directed back into the first medium. This effect is called total internal reflection, and it occurs whenever the refractive index of the first media is higher than the second media $n_{1}$ \> $n_{2}$.  > [!Figure] > _Illustration of Snell's Law showing how an incident light ray is bent as it travels across the interface of two materials with different refraction index_ Now, imagine if we sandwich the high index glass between two slabs of lower index glass, as shown in the figure below. Because total internal reflection occurs at both surfaces, the light bounces back and forth between them and is guided through the middle piece of glass. This is a basic optical waveguide. We can extend this approach by constructing a glass fiber, with a higher refractive index material surrounded by a lower refractive index material. Since the fiber core has a higher index of refraction than the surrounding cladding, there is a critical angle, $\theta_{c}$, where incident light will be reflected back into the fiber and guided along the core.  > [!Figure] > _A sandwich of glass slabs with different indices of refraction used to guide light rays_ The critical angle is given by the following equation: $\large \theta_{c} = \ \sin^{- 1}\left( \frac{n_{2}}{n_{1}} \right)$ Thus, if we make a fiber with a higher refractive index in the core and surround it with a lower index material as the cladding, then launch light waves at less than the critical angle, the light will be totally reflected every time it strikes the core-cladding interface. In this way, the light will travel down the fiber, following it around fairly tight corners or other bends. In practice, the fiber will also have an outer coating or jacket to add strength, since the fibers themselves are very small. For typical fibers used in communication systems, the refractive index difference between the core and the cladding is about 0.002-0.008.  > [!Figure] > _A cylindrical strand of glass with a higher index core forms an optical fiber_ This is a simplified picture of how light travels, which is useful to help us understand how an optical fiber works. For a more complete, accurate picture, we must realize that light is an electromagnetic wave, and an optical fiber is a dielectric optical waveguide. Light propagation follows Maxwell's equations which describe all types of electromagnetic fields. To describe an optical fiber, we can begin with these equations and derive the wave equation, which is a partial differential equation that can be solved using the boundary conditions in a cylindrical fiber. The mathematics is fairly complex and yields expressions for the electromagnetic field of light in the fiber with a finite number of propagation modes. For our purposes, we will continue using the simplified, geometrical model of fibers. If the fiber shown previously has a large core diameter, light can enter from many different angles. Each of these will take a different path through the fiber. We can loosely call these different paths modes of propagation; if we use the more rigorous Maxwell's equations, they would correspond to the different propagation modes of electromagnetic waves in a bounded waveguide. Fibers with a large core can support several modes of propagation and are called multimode. There are several standard fiber core diameters used for communication systems, including 62.5-micron fiber (sometimes called "FDDI grade," since it was originally specified for an industry standard called Fiber Distributed Data Interface) and 50 microns. The cladding diameter for communication fiber is typically 125 microns, and for other fibers, it may be around 140 microns. Fibers are often specified with both their core and cladding sizes; for example, we can speak of "50/125" and "100/140" fiber. Multimode fiber distances are limited by interference between the different modes, sometimes called modal noise. Different modes will travel different distances along the fiber core, so even if they are launched into the fiber at the same time, they will not emerge together. This is called multipath time dispersion. If we send a pulse of light into the fiber, this pulse will spread out as it travels because of time dispersion. A high-speed digital communication channel is just a sequence of pulses (for example, the digital "1" and "0" of a computer signal can be represented as a light pulse turned on or off). As we try to send higher and higher data rate signals, the pulses being launched into the fiber become narrower and closer together. Eventually, dispersion will make these pulses spread out so that they overlap, and it becomes impossible to tell one pulse from another. In this way, we see that increasingly higher communication data rates can only be supported over shorter and shorter lengths of multimode fiber. Put another way, the maximum useful bandwidth of the fiber, or the maximum bit rate for digital communications, is inversely related to the time dispersion. Multimode fiber is specified with a bandwidth-distance product written on the cable, for example, 500 MHz-km; this means that an optical signal modulated at 500 MHz can travel up to 1 km before dispersion (and other effects) corrupt the signal beyond recognition. Similarly, an optical signal at half this speed (250 MHz) could go twice the distance (2 km). We have simplified this discussion, but time dispersion between different fiber modes places a fundamental limit on the fiber bandwidth. On the other hand, the reason we are interested in optical fibers for communication is because their available bandwidth far exceeds that of copper wire. As the fiber core grows smaller, fewer and fewer modes can propagate. Fibers with a smaller core (8--10 microns) that support essentially only one mode of propagation are called single mode. They use laser sources and can go further unamplified distances ∼ 20-50 km), because they do not have modal noise issues. Single-mode fibers do not have a bandwidth-distance product specification; their working distance is limited by other factors, such as signal loss or attenuation. When specifying a fiber link, simplex refers to a one-directional link; a duplex, which uses two fibers, is required for two-way communication; it is possible to design duplex links using different wavelengths. From a transmission point of view, the two most important fiber parameters are bandwidth and attenuation. The fundamental reason for using fiber instead of copper cable is the increased bandwidth. Bandwidth is tested using a very fast laser and a sensitive receiver. A software analyzes the difference between the input and the output pulses and calculates the bandwidth of the fiber. Bandwidth is inversely proportional to dispersion (pulse spreading), with the proportionality constant dependent on pulse shape and how bandwidth is defined. We have already mentioned that single-mode fiber is used at longer distances because it does not have intermodal dispersion. Other forms of dispersion are material dispersion (because the index of refraction is a function of wavelength) and waveguide dispersion (because the propagation constant of a fiber waveguide is a function of wavelength). Attenuation is a decrease in signal strength caused by absorption, scattering, and radiative loss. #### Transmitters In fiber optic links, different types of transmitters can be used. The most typical types of transmitters are LEDs, lasers, and optical modulators. LEDs are frequently used for multimode fiber optic links. The two types of LEDs, surface-emitting LEDs and edge-emitting LEDs (ELEDs), have a high divergence of the output light (meaning that the light beams emerging from these devices can spread out over 120 degrees or more); slow rise times (>1 ns) that limit communication to speeds of less than a few hundred MHz; and output powers on the order of 0.1-3 mW. However, LEDs are less temperature-sensitive than lasers and are very reliable. For higher data rates, laser sources at short wavelengths (780-850 nm) are typically used with multimode fiber, and longer wavelengths (1.3-1.5 microns) with single-mode fiber. Typical lasers used in communications systems are edge-emitting lasers (light emerges from the side of the device), including double heterostructure (DH), quantum well (QW), strained layer (SL), distributed feedback (DFB), and distributed Bragg reflector (DBR). Vertical cavity surface emitting lasers (VCSELs) have been introduced for short wavelength applications and are under development for longer wavelengths; fibers may couple more easily to these surface emitting sources. Compared with LEDs, laser sources have much higher powers (3-100 mW or more), and narrower spectral widths. #### Detectors and Receivers An optical receiver includes both the optical detectors, or photodetectors (the solid state device that converts an optical signal to an electrical signal), and various electronic circuits such as amplifiers or clock recovery circuits. Typical devices used for this goal are semiconductor devices such as PIN photodiodes, avalanche photodiodes (APD), photodiode arrays, Schottky-Barrier photodiodes, metal-semiconductor-metal (MSM) detectors, resonant-cavity photodetectors, and interferometric devices. APDs are used in high-sensitivity applications, MSM photoconductive detectors are sometimes used because of their ease of fabrication, and Schottky-barrier photodiodes are used for high-speed applications. Resonant-cavity photodetectors are not commonly used anymore but have potential for future development. Other types of detectors are also becoming more common in applications such as wavelength division multiplexing (WDM) and parallel optical interconnects (POI). It is worth noting that fiber optic systems typically package transmitters and receivers in a single housing known as transceivers (TRX). These are used for most two-fiber bi-directional communication links. Depending on the application, more or less electronics may be packaged within a transceiver. Detectors are an integral part of all fiber optic communication systems. They convert a received optical signal into an electrical signal, demodulating the optical signal that was modulated at the transmitter. This initial signal may be subsequently amplified or further processed. Optical detectors must satisfy stringent requirements such as high sensitivity at the operating wavelengths, fast response speed, and minimal noise. #### Optical Interconnects in PCBs Applications in telecommunications, defense, autonomous vehicles, and aerospace systems that require massive data transfer rates already make extensive use of fiber optics for embedded computing. However, the interfacing between optical and electrical physical layers has never been the most optimal, usually employing bulky connectors and transceivers to interface semiconductors with optical transceiver modules. As technologies like Silicon photonic integrated circuits (PICs) and electronic-photonic integrated circuits (EPICs) gain maturity, they are gently asking for a new era of coupling methods between optical signals with classic processing like System-on-Chips and FPGAs. A new physical interconnect architecture will be needed to route optical signals in an assembly without using bulky transducers. How deep can we expect optical interconnects to penetrate PCBAs? Research over recent decades has looked at bringing optical interconnects directly into the PCB. One option for optical interconnects in PCBs is to embed glass fibers in the interior layers of a multilayer PCB. The other option is to deposit polymer waveguides on the interior layers or surface layers. Glass fibers could also be placed on the surface layer, but using polymers allows greater control over geometry. This becomes important for interfacing with optical components as the geometry and coupling optics must be precisely defined on the surface layer. Glass optical interconnects will likely be easiest to integrate into standard multilayer [[#Board Manufacturing|PCB manufacturing processes]] as they can be embedded in the core or prepreg layers. The right material between FR4 laminates can act as a cladding layer for glass waveguides. There is no reason that glass or polymers could not be used simultaneously; standard glasses for optical fibers can be used in the inner layer, while polymers would be easiest to deposit on the outer layer. An alternative to this would be to use polymer waveguides. Transparent polymers for use in optical waveguides at infrared or visible wavelengths have been demonstrated in the literature as early as 2001. Prior work focused on more general materials development and the use of optical glass in innovative ways. Polymer waveguides are a major advantage over glass waveguides for several reasons: - Polymers can have tunable optical properties for usage at different wavelengths - Polymers can be layered with refractive index contrast, giving total internal reflection - Polymers can be incorporated into planar photolithography and etching processes - Optical loss and dispersion in polymers are competitive with the values found in optical fibers Polymer waveguides would be used on the surface layer so that they have direct access to electro-optical modules and PICs/EPICs. However, they have also been studied for use in the internal layers of a PCB, similar to having an optical interconnect layer made from embedded optical fiber. The image below shows some coupling methods for polymer waveguide optical interconnects in a PCB. These are most likely to be used on a surface layer through an interface with a PIC/EPIC package.  > [!Figure] > _Various coupling methods used for polymer waveguides on PCB substrates: (a) grating coupling, (b) evanescent wave coupling, (c) out-of-plane micro-mirror coupling, and (d) end-fire coupling._ Throughputs up to 1Tbps per printed circuit board (PCB) have been experimentally demonstrated[^27] using 1000 channels per PCB with a 1mm optical beam array at 1 Gbps per channel. ### Free Space Optical Communication Although we stated at the beginning of the text that this text would strictly focus on wired signals, we will take a brief detour here to discuss wireless optical communications (WOC). WOC communication is considered the next frontier for high-speed broadband connection due to its unique features: very high bandwidth, ease of deployment, tariff-free bandwidth allocation, low power (roughly half of radio frequency (RF) systems), less mass (roughly half compared with RF systems), small size (10% the diameter compared to an RF antenna), and improved channel security. It has emerged as a good commercial alternative to existing radio-frequency communication as it supports larger data rates and provides high gain due to its narrow beam divergence. It is capable of transmitting data up to 10 Gbps and voice and video communication through the atmosphere/free space. WOC has two broad categories, namely, indoor and outdoor wireless optical communications. Indoor WOC is classified into four generic system configurations, i.e., directed line-of-sight (LOS), non-directed LOS, diffused, and quasi diffused. Outdoor wireless optical communication is also termed free-space optical (FSO) communication. Free space optical communication finds wide application in space. A reality that many space companies face every day is data bottlenecks. Satellites generate lots of data—a single acquisition from a camera or a radar can account for several gigabytes of raw data, creating terabytes of payload data per day. According to the European Space Agency (ESA), the Sentinel-1 radar satellite produces approximately 10 terabytes (TB) of data per day, while the Sentinel-2 multispectral instrument generates around 20 TB of data per day[^28]. Another example is Landsat 8, a joint mission of NASA and the United States Geological Survey (USGS), which captures images of the Earth's surface at a spatial resolution of 30 meters. Landsat 8 generates approximately 700 scenes per day, with each scene covering an area of about 185 kilometers by 185 kilometers. Each scene contains approximately 700 megabytes (MB) of data, which adds up to approximately 500 gigabytes (GB) of data per day[^29]. But the real deal is how to make sure this amount of data gets to the right hands as fast as possible. On-board storage is not infinite, and more importantly, customers are having problems that are waiting to be solved with the help of geospatial data. Space systems have historically relied on radio links to transfer data to the ground stations, and to end users. Radio links have known drawbacks: interference, noise, and spectrum sharing. These are all somewhat intertwined. The main problem with RF channels is that there is no such thing as a true point-to-point radio link. This means, one ideal transmitting antenna sending electromagnetic photons to be exclusively captured by a distant receiving entity. In reality, there are scattered photons all over the place. Statistically, a substantial number of photons will arrive at the intended receiving entity and the signal will be hopefully reconstructed, what happens with nomad radio photons that go elsewhere? That is the key here. We as humans have managed to create billions of radiating/transmitting artifacts around the world, all of them scattering photons outside of their ideal boundaries, creating a soup of radio waves wandering around, getting where nobody called them, and knocking on the door at the wrong antennas. As we also described before, there are human-made transmitting devices that are not purposely meant to be radio transmitters—a car engine starting spreads radio energy in many different bands with various energies; such radio energy is a by-product of the workings of internal electric devices of the engine such as spark plugs, electric motors, etc. Transmitting and receiving antennas have their own spatial preference when it comes to collecting radio quanta—they collect more from some directions than others—and such preference is never laser-focused. For any receiving antenna collecting "right" and "wrong" electromagnetic energy, we can call the former signal and the latter noise. The proportion between these two is the already familiar signal-to-noise ratio. Due to the spectrum coordination needs we talked about in the previous section, every satellite carrying a radio transmitter requires approval from the International Telecommunications Union, or ITU. Such a need for coordination does not come without its dose of bureaucracy. As more and more actors are coming into the space industry, with shorter timelines and the determination to rapidly get into the market, the radio licensing process can be slow and cumbersome. Radio links are constantly getting better as the technology matures, but the main downsides—notably interference and compliance—are still there and will be there. The alternative to this? Optical communications. But why use light? Optical communication is not regulated by the International Telecommunication Union, which means it can be used without restrictions and does not require licensing. The reason for this should be clear by now: optical links are comparatively more focused than radio links—they have small beamwidths, and incredibly high bandwidths—which means that between transmitter and receiver, fewer photons are going astray. How? Optical transmitters produce a narrow beam of light in which all of its composing waves have very similar wavelengths, and they travel together in phase—the emitted photons are \" in step" and have a definite phase relation to each other—concentrating a lot of energy on a very small area. As there is no such thing as a free lunch, adding optical communications to satellites does not come without certain challenges. Because the light beamwidths are so narrow, this requires that the pointing capabilities of the satellites carrying optical terminals be top-notch. What is more, satellites have to be structurally optimized to carry the highly sensitive optical equipment, reducing, and filtering mechanical jitter and unwanted vibrations, which requires sound structural analysis and design to precisely understand how the vibrations find their paths across the satellite's structure. Last but not least, the onboard data handling architecture must be up to the task by allowing the high data rate frames to seamlessly flow from the optical terminal to the onboard resources such as processing units and data recorders, and vice versa. Another important property of laser communications is that their beams cannot pass through solid/opaque objects. Hence, manmade structures on Earth as well as cloud cover can cause some attenuation in earth-to-space communications. However, it is not a major deterrent and can be overcome with careful planning and consideration. More importantly, there are no such hurdles in space-to-space communications, and hence laser technology is ideal for inter-satellite links and other space-based communication. There is quite some activity in the laser comms sector happening at the moment[^30]. NASA demonstrated an optical link from the Moon in 2018 with the Lunar Laser Communications Demonstration (LLCD). The LLCD demonstration consisted of a space terminal on the LADEE spacecraft[^31] and three ground terminals on Earth. Together, they demonstrated that it was possible to transfer up to 622 Mbps (megabits per second) of data from the Moon with a space terminal that weighs less, uses less power, and occupies less space than a comparable RF system[^32]. Commercial actors in the market are increasingly incorporating laser terminals in their constellations[^33]. Based on their transmission range, wireless optical communication (WOC) can be classified into five broad categories: 1. Ultrashort-range WOC: used in chip-to-chip communication or all-optical lab-on-a-chip system. 2. Short-range WOC: used in wireless body area networks (WBANs) or wireless personal area networks (WPANs). 3. Medium-range WOC: used in indoor IR or visible light communication (VLC) for wireless local area networks (WLANs) and inter-vehicular and vehicle-to-infrastructure communications. 4. Long-range WOC: used in terrestrial communication between two buildings or metro area extensions. 5. Ultra-long-range WOC: used in ground-to-satellite/satellite-to-ground or inter-satellite link or deep space missions. This is the one we will expand in this section. #### Atmospheric Channel The concentric layers around the surface of the Earth are broadly classified into two regions: homosphere and heterosphere. The homosphere covers the lower layers ranging from 0-90 km. The heterosphere lies above the homosphere above 90 km. The homospheric region of the atmosphere is composed of various gases, water vapors, pollutants, and other chemicals. Maximum concentrations of these particles are near the Earth's surface in the troposphere which extends up to 20 km. The figures below depict the broad classification of various layers of the atmosphere, along with details of each layer and their temperature. The density of particles decreases with the altitude up through the ionosphere (region of the upper atmosphere that extends from about 90 to 600 km and contains ionized electrons due to solar radiations). These ionized electrons form a radiation belt around the surface of the Earth. These atmospheric particles interact with all signals that propagate through the radiation belt and lead to deterioration of the received signal due to absorption and scattering. Absorption is the phenomenon where the signal energy is absorbed by the particles present in the atmosphere resulting in the loss of signal energy and gain of internal energy of the absorbing particle. In scattering, there is no loss of signal energy like in absorption, but the signal energy is redistributed (or scattered) in arbitrary directions.  > [!Figure] > *Broad classification of atmosphere layers. Source: #ref/Gagliardi*  > [!Figure] > *Broad classification of atmosphere layers. Source #ref/Gagliardi* Both absorption and scattering are strongly dependent upon the operating wavelength and will lead to a decrease in the received power level. These effects become more pronounced when the operating wavelength of the transmitted signal is comparable with the cross-sectional dimensions of the atmospheric particles. The figure below shows attenuation effects as a function of wavelength.  > [!Figure] > _Transmittance (attenuation) vs wavelength_  > [!Figure] > _Average droplet size_ It is clear from the figure below on attenuation that peaks in attenuation at specific wavelengths are due to absorption by atmospheric particles and therefore the choice of wavelength has to be done very wisely in the high transmissive band for FSO communication links. The atmospheric condition in the FSO channel can be broadly classified into three categories, namely, clear weather, clouds, and rain. Clear weather conditions are characterized by long visibility and relatively low attenuation. Cloudy weather conditions range from mist or fog to heavy clouds and are characterized by low visibility, high humidity, and large attenuation. Rain is characterized by the presence of rain droplets of variable sizes, and it can produce severe effects depending upon rainfall rate. Various atmospheric conditions can be represented by the size of the particle (i.e., cross-sectional dimension relative to operating wavelength) and the particle density (i.e., volumetric concentration of the particles). The figure above shows the average droplet size and its distribution for various cloudy and rainy conditions. It is seen that conditions may vary from high density and small particle size like in the case of mist and fog to low density and large particle size during heavy rain. It should be noted that the figure gives average parameters, whereas real atmospheric conditions may undergo various temporal changes. #### Atmospheric Losses ##### Absorption and Scattering Losses The atmospheric channel consists of various gases and other tiny particles like aerosols, dust, smoke, etc., suspended in the atmosphere. Besides these, large precipitation due to rain, haze, snow, and fog is also present in the atmosphere. Each of these atmospheric constituents results in the reduction of the power level, i.e., attenuation of optical signal due to several factors, including absorption of light by gas molecules, Rayleigh, or Mie scattering. Various types of losses encountered by the optical beam when propagating through the atmospheric optical channel are briefly described here. Losses in the atmospheric channel are mainly due to absorption and scattering processes. At visible and IR wavelengths, the principal atmospheric absorbers are the molecules of water, carbon dioxide, and ozone. The wavelength range of FSO communication systems is chosen to have minimal absorption. This is referred to as atmospheric transmission windows. In this window, the attenuation due to molecular or aerosol absorption is less than 0.2 dB/km. There are several transmission windows within the range of 700-1600nm. The majority of FSO systems are designed to operate in the windows of 780-850 and 1520-1600 nm. The scattering process results in the angular redistribution of the optical energy with and without wavelength change. It depends upon the radius $r$ of the particles encountered during the propagation process. If $r\ < \ \lambda$, the scattering process is classified as Rayleigh scattering; if $r\ \approx \ \lambda$, it is Mie scattering. For $r\ > \ \lambda$, the scattering process can be explained using the diffraction theory (geometric optics). Out of various scattering particles like air molecules, haze particles, fog droplets, snow, rain, hail, etc., the wavelength of fog particles is comparable with the wavelength of the FSO communication system. Therefore, it plays a major role in the attenuation of an optical signal. ##### Free Space Losses In an FSO communication system, the largest loss is usually due to "space loss," i.e., the loss in the signal strength while propagating through free space. The space loss factor is given by: $\large L_{s} = \ \left( \frac{\lambda}{4\pi R\ } \right)^{2}$ where $R$ is the link range. Due to dependence on wavelength, the free-space loss incurred by an optical system is much larger (i.e., the factor $L_{S}$ is much smaller) than in an RF system. Besides the space loss, there are additional propagation losses if the signal passes through a lossy medium, e.g., a planetary atmosphere. Many optical links like deep space optical links do not have additional space loss as they do not involve the atmosphere. ##### Loss Due to Weather Conditions The performance of an FSO link is subject to various environmental factors like fog, snow, rain, etc. that lead to a decrease in the received signal power. Out of these environmental factors, the atmospheric attenuation is typically dominated by fog as the particle size of fog is comparable with the wavelength of interest in an FSO system. It can change the characteristics of the optical signal or can completely hinder the passage of light because of absorption, scattering, and reflection. Atmospheric visibility is a useful measure for predicting atmospheric environmental conditions. Visibility is defined as the distance that a parallel luminous beam travels through in the atmosphere until its intensity drops 2% of its original value. To predict the optical attenuation statistics from the visibility statistics for estimating the availability of the FSO system, the relationship between visibility and attenuation has to be known. ##### Beam Divergence Loss As the optical beam propagates through the atmosphere, it spreads out due to diffraction. It may result in a situation in which the receiver aperture is not able to collect a fraction of the transmitted beam resulting in beam divergence loss. #### Optical Terminals for Space Applications Optical Terminals, also called Laser Comm Terminals (LCTs), are composed of two main elements: an optical head and a controller, each assigned with clear roles. The optical head has its own internal composition, but basically, it is a mechatronic assembly that performs the necessary functions to spatially control the orientation of the transmitter/receiver for maintaining a free space optical (FSO) communication link. The optical head does this by means of implementing a two-axis gimbal providing movement in azimuth and elevation. Optical heads have two levels of orientation control: coarse and fine. The coarse function aims to provide the initial conditions for the link to close (using the gimbal), whereas the fine functionality aims to keep the link stable using closed-loop control for the data to be modulated/demodulated and transferred to the controller and to the system (utilizing controlling mirrors in the telescope assembly). The controller unit interfaces with the rest of the host system, performs configuration of the subsystem, > [!Warning] > This section is under #development ## Connectors When discussing the physical layer in data interfaces, we must not forget about connectors. There is not perhaps a more neglected, overlooked member in every digital system's hierarchy than the connector. Connectors are the ultimate physical barrier in digital systems, defining what can and what cannot connect to the system it belongs to. If anything, this section is an ode to this essential, although criminally underrated component. Connectors allow circuits and products that are manufactured independently to be electrically connected, tested, maintained, and upgraded.  > [!Figure] > _Parts of a connector_ The figure above depicts the typical parts of a connector. The contact spring provides the path for the transmission of a signal, power, and/or ground between the circuits that the connector connects. It also provides the normal force, the component of the force that is perpendicular to the surface of contact, which helps in the formation and maintenance of the separable interface in a way that does not become loose. The key mechanical requirements of the contact spring are insertion and extraction force, contact force, contact retention, and contact wipe. The electrical requirements of the contact spring are contact resistance, current rating, inductance, capacitance, and bandwidth. A separable interface is established each time the "male" and "female" parts of the connector are brought into contact. There is a need to create and maintain contact interfaces to achieve the desired electrical performance. The metallic interface is created mechanically.\ When separable connectors are mated, only the high spots on the surfaces, which are called "asperities," come into contact. Therefore, the entire connector surface does not come into contact. The asperities depend on the geometry of the surfaces in contact.  > [!Figure] > _Contact interface_ The figure above depicts a normal contact interface. It can be seen that only the asperities of both surfaces come into contact. The size and the number of asperities depend on the surface roughness and the applied load. The applied load also determines the magnitude of the contact area. The structure of the contact interface depends on the roughness of the surface (which influences the number of asperities), the applied force, and the contact interface geometry. The mechanical characteristics of the contact interfaces, particularly the frictional and wear forces, depend on the asperity microstructure of the contact interfaces.  > [!Figure] > _Schematic illustrations of (a) mating and engagement process and (b) characteristic curve for insertion force_ The evolution of electronics toward higher speeds and switching frequencies has enforced stringent requirements on connectors. The challenges that confront connectors are extra electrical length, the need for a larger assembly area, compatibility with new technologies, and reliability concerns. Although connectors are ideally transparent electrically speaking, they are not. A connector introduces an extra electrical path that can lead to added propagation delay and signal integrity issues such as cross-talk. A connector also introduces concerns for reliability because degradation of the contact interface can lead to an increase in contact resistance, which can lead to signal degradation, joule heating, and power loss. These losses are due to increases in contact resistance, which is dependent on the material properties of the connectors, environmental conditions, and mode of operation. Furthermore, because a connector occupies more area than a simple solder or adhesive, the use of connectors might be difficult in applications that have area constraints. Connectors are designed to join interconnects, forming an electrical circuit and ensuring a reliable flow of energy or data. The world of electronic connectors is vast and varied, encompassing a wide range of designs, sizes, and functionalities to cater to diverse applications, from DC to microwaves and beyond. Connectors can be broadly categorized into three types: - Cable-to-cable connectors: connectors of this kind connect two wires, as the name suggests. One end of the connector is permanently connected to the cable. The other end of the connector forms a separable interface. - Board-to-board connectors: Board-to-board connectors are used to directly connect PCBs without a cable. The board-to-board connectors can save space on cables, making them suitable for systems with limited space (see next two figures). These are used in [[Backplanes and Standard Form Factors#Mezzanines|mezzanines]], carrier boards and [[Backplanes and Standard Form Factors|backplanes]]. - Board-to-cable connectors: A wire-to-board connector connects a wire/cable to a PCB. The wire connections are similar to the one used for wire-to-wire connection, and the board connections are, for the most part, press-in or soldered two-piece connectors, although some card edge versions remain in use. The mating interface for the separable connection may be identical to that of a wire-to-wire connector from the same product family.  > [!Figure] > _Board-to-board connector_  > [!Figure] > _A backplane system_ Therefore, as the frequencies used in electronic devices increase, connectors face unique challenges. High-frequency signals are more susceptible to loss and interference, requiring connectors to have excellent signal integrity. This means that connectors must be designed to minimize signal degradation, crosstalk, and electromagnetic interference (EMI). At higher frequencies, even small imperfections in the connector can have a significant impact on performance. The materials used, the geometry of the connector, and the quality of the connection all play a critical role in maintaining signal integrity. Additionally, as electronic devices become more compact and the demand for miniaturization grows, connectors must adapt by becoming smaller while still maintaining their functionality and reliability. This miniaturization adds complexity to the design and manufacturing of connectors, as they must handle high-speed signals without compromising performance or increasing the risk of degrading the signal integrity. In any electronic system, six levels of interconnection are normally seen in connectors (illustrated in the figure below): - Level 0: is the connection between a semiconductor die and its lead. Usually, this interconnection is inaccessible to the designer of the product. - Level 1: is the connection between a component lead and a printed circuit board (PCB). From this level on, designers potentially have physical access. - Level 2: is the connection between two or more PCBs, for instance between a mezzanine board and a carrier board or a backplane. - Level 3: is the connection between two internal subassemblies within the same unit, such as a power supply and a board, or a controller and a mass memory unit. - Level 4: is the connection from a major subassembly to the input/output (I/O) port as seen from the housing of the complete system. - Level 5: is the connection between physically separated units typified by the link between a unit and a piece of peripheral equipment (for instance, a flight computer and a sensor), or between nodes in a local network.  > [!Figure] > _Levels of interconnection in a unit_ Backplane connectors like the MultiGig RT2 used in [[Backplanes and Standard Form Factors#VPX|VPX]] use PCB wafer connectors. They are typically composed of a series of conducting wafers or blades that make electrical contact with corresponding slots or receptacles on the component they are connected to. ## On-Die Interconnects ### Elements A typical silicon die will have up to five different interconnect elements: - Lines: The lines form the most obvious type of interconnect, carrying signals short or long distances across a die. They’re formed from a metal or a combination of metals. The routing freedom depends on the process generation. Multiple layers can carry lines, separated by a dielectric. Advanced nodes can have as many as 15 layers. - Vias: Vias connect the lines on one layer to those on another. They are also formed from metals or metal combinations. - Local interconnect: This is a special layer of interconnect that’s more typically made of doped polysilicon. It connects transistor terminals right above the transistors, below the metal layers. Different foundries may build it differently, and details tend to be unavailable to the public. - Contacts: These are openings in the dielectric right above active silicon where metal connects to transistors. They reside below the bottom metal layer and may be contacted by standard metal lines or local interconnect. - Through-silicon vias (TSVs): These are vias that go from a metal layer on the front side of the wafer to the back side, not from metal layer to adjacent metal layer. They’re critical for bringing connections to the back of the wafer when bonding a die face-up in a package. - Bond pads: These are metal pads exposed to the outside world. They provide a place to attach bond wires or bumps/balls. - Balls or bumps: These are the means of mounting a die using surface-mount technology instead of wire bonds. The balls are made of solder rather than copper or aluminum. ![[Pasted image 20250904095427.png]] >[!figure] >*Basic on-die interconnect elements. Lines carry signals across the die; vias carry them between line layers. Local interconnect connects transistor contacts at the lowest level above the active devices fabricated at the front-end of line (FEoL). Contacts allow connection of metal layers to active devices such as transistors. Those metal layers are fabricated as the back-end-of-line (BEoL). Through-silicon vias (TSVs) carry signals through the bulk of the wafer to the back side.* ## Cabling No discussion about digital systems and data interfaces would be even remotely complete without discussing cabling. Cables connect boards, units, racks, and...continents. The importance of reliable cabling could not be stressed enough. Data cabling typically accounts for less than 10 percent of the total cost of the network infrastructure. Also, cables last long: the life span of the typical network cabling system is upward of 16 years. Cabling is likely the second most long-lived asset you have in a data center (the first being the shell of the building). All this being said, a very high percentage of network-related problems are due to poor cabling techniques and cable-component problems. In traditional network installations, the most economical and widely installed cabling today is twisted pair wiring. Not only is twisted-pair wiring less expensive than other media, but installation is also simpler, and the tools required to install it are not as costly. Unshielded twisted-pair (UTP) and shielded twisted-pair (STP) are the two primary varieties of twisted-pair on the market today. Screened twisted-pair (ScTP) is a variant of STP. Cabling tends to be categorized into horizontal and vertical cabling. Horizontal cabling refers to the wiring that extends from the telecommunications outlet in the work area to the horizontal cross-connect in the telecommunications room or enclosure. It's typically used within a single floor of a building. This type of cabling is used to connect devices like computers, phones, and other network devices to the main telecommunications room. The horizontal cabling is usually done with twisted pair, fiber optic, or coaxial cables and is limited in length to ensure signal integrity. Vertical cabling, also known as backbone cabling, is used to connect different floors or buildings in a network. It connects the equipment rooms and telecommunications rooms within a building or across multiple buildings. This type of cabling typically includes larger transmission media, like fiber optic cables, and is capable of carrying more data over longer distances compared to horizontal cabling. The backbone cabling is essential for the overall network infrastructure as it provides the main path for data traffic across different network segments. Though it has been used for many years for telephone systems, unshielded twisted-pair (UTP) for LANs first became common in the late 1980s with the advent of Ethernet over twisted-pair wiring and the 10Base-T standard. UTP is cost-effective and simple to install, and its bandwidth capabilities are continually being improved. UTP cabling typically has only an outer covering (jacket) consisting of some type of nonconducting material. This jacket covers one or more pairs of wires that are twisted together. Unless specified otherwise, a UTP cable is typically a four-pair cable. The characteristic impedance of UTP cable is 100 ohms plus or minus 15 percent, though 120 ohm UTP cable is sometimes used in Europe and is allowed by the ISO/IEC 11801 Ed. 2.2 cabling standard. A typical UTP cable is shown in. This simple cable consists of a jacket that surrounds four twisted pairs. Each wire is covered by an insulation material with good dielectric properties. For data cables, this means that in addition to being electrically nonconductive, it must have certain properties that allow good signal propagation. Shielded twisted-pair (STP) cabling was first made popular by IBM when it introduced type classification for data cabling. STP cable is less susceptible to outside electromagnetic interference (EMI) than UTP cabling because all cable pairs are well-shielded.  > [!Figure] > _UTP Cable_  > [!Figure] > _Shielded Twisted Pair_ Needless to say, simply installing STP cabling does not guarantee it will improve a cable's immunity to EMI or reduce the emissions from the cable. Several critical conditions must be met to achieve good shield performance: - The shield must be electrically continuous along the whole link. - All components in the link must be shielded. No UTP patch cords can be used. - The shield must fully enclose the pair, and the overall shield must fully enclose the core. Any gap in the shield covering is a source of EMI leakage. - The shield must be grounded at both ends of the link. If even one of these conditions is not satisfied, shield performance will be badly degraded. If the shield continuity is broken, the emissions from a shielded cabling system increase considerably.  > [!Figure] > _top: 4-pair unshielded twisted pair; middle: 2-pair shielded twisted pair; bottom: 2-fiber multimode optical fiber)_ ANSI/TIA-568-C specifies the signal integrity specs for network cables of several categories. > [!warning] > This section is under #development [^12]: The wavelength of an electromagnetic wave is inversely proportional to its frequency, meaning as frequency increases, wavelength decreases, according to the relationship $c\ = \ \lambda f$, where $c$ is the speed of light, $\lambda$ is the wavelength, and $f$ is the frequency. [^13]: In more physical terms, the divergence represents how much a vector field like the electric field is spreading out or converging at a given point in space. In a sense, the divergence marks the presence of sinks or sources in said vector field. [^14]: The curl operator $\text{(}\nabla \times \text{)}$ measures the tendency of a vector field to rotate around a point. [^15]: Jitter is a complex topic in digital communications, and there are different types of jitter present in digital signals. See chapter 2 in "*High Speed Digital Design of High Speed Interconnects and Signaling*" by Hanqiao Zhang, Steven Krooswyk and Jeff Ou (Elsevier). [^16]: An application note from TDA Systems explains the measurement procedure: https://download.tek.com/document/DIEC-0502-01.pdf [^17]: One exception being are saturated ferrites. [^18]: The unit interval is the time slot allocated for one bit of information in a serial data transmission. [^19]: https://api.pim.na.industrial.panasonic.com/file\_stream/main/fileversion/244767 [^20]: https://www.signalintegrityjournal.com/articles/1771-a-simple-demonstration-of-where-return-current-flows [^21]: Note there are no links available to this publication, to the best of my knowledge [^22]: Root Mean Square (RMS) is a statistical measure used in various fields, including mathematics, physics, electrical engineering, and signal processing which is particularly useful when handling alternating quantities; the RMS value provides a way to quantify these alternating quantities in terms of an equivalent steady value that would produce the same effect. [^23]: https://www.edn.com/how-much-common-current-is-too-much-rule-of-thumb-31/ [^23]: https://www.edn.com/how-much-common-current-is-too-much-rule-of-thumb-31/ [^24]: http://smbus.org/ [^25]: https://pmbus.org/ [^26]: https://ww1.microchip.com/downloads/aemDocuments/documents/VOP/ApplicationNotes/ApplicationNotes/Signal+Types+and+Terminations.pdf [^27]: https://ui.adsabs.harvard.edu/abs/1998OptEn..37.1332H/abstract [^28]: Retrieved from <https://sentinel.esa.int/web/sentinel/sentinel-data-access> [^29]: Retrieved from <https://www.usgs.gov/media/files/landsat-8-data-users-handbook> [^30]: <https://www.nasa.gov/feature/goddard/2021/laser-communications-empowering-more-data-than-ever-before> [^31]: <https://www.nasa.gov/mission_pages/ladee/main/index.html> [^32]: <https://www.nasa.gov/directorates/heo/scan/opticalcommunications/llcd/> [^33]: <https://spacenews.com/all-future-starlink-satellites-will-have-laser-crosslinks/>